Improving the Scalability of Ferroelectric FET Nonvolatile Memories With High-k Spacers

You Sheng Liu, Pin Su*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


This paper investigates scaled ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) with high-k spacer device design considering ferroelectric-dielectric random phase variations with TCAD atomistic simulations. Our study indicates that, in addition to raising the orthorhombic phase and reducing the grain size of the ferroelectric, using high-k spacers can serve as another way to enhance the scalability of FeFETs because it improves both the mean memory window (MW) and the worst-case MW. More importantly, these improvements increase with the down-scaling of gate length. In addition, we have investigated the impact of high-k spacers on the critical electric field across interfacial layer (EIL) for the reliability of FeFET NVMs. Our study suggests that, for scaled FeFETs with high-k spacers, the highest EIL during write operation is no longer located near the S/D edge but at the mid channel. Using high-k spacers can reduce the mid-channel EIL, and the reduction increases with decreasing gate length due to the increasing impact of high-k spacers. Our study may provide insights for future high-density FeFET design.

Original languageEnglish
Pages (from-to)346-350
Number of pages5
JournalIEEE Journal of the Electron Devices Society
StatePublished - 2022


  • Ferroelectric field-effect transistor (FeFET)
  • Memory window (MW)
  • Nonvolatile memory (NVM)


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