Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

Catherine Langpoklakpam; An Chen Liu; Neng Jie You; Ming Hsuan Kao; Wen Hsien Huang; Chang Hong Shen; Jerry Tzou; Hao Chung Kuo; Jia Min Shieh

doi:10.3390/mi14030576

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

Catherine Langpoklakpam, An Chen Liu, Neng Jie You, Ming Hsuan Kao, Wen Hsien Huang, Chang Hong Shen, Jerry Tzou, Hao Chung Kuo^*, Jia Min Shieh

^*Corresponding author for this work

Department of Photonics

Research output: Contribution to journal › Article › peer-review

Abstract

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from −0.85 V to −0.74 V after applying a high gate bias stress at 150 °C for 10⁻² s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device’s reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

Original language	English
Article number	576
Journal	Micromachines
Volume	14
Issue number	3
DOIs	https://doi.org/10.3390/mi14030576
State	Published - Mar 2023

Keywords

gallium nitride
HTGB
low thermal budget gate first process
ohmic contact
power device

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10.3390/mi14030576

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title = "Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs",

abstract = "In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from −0.85 V to −0.74 V after applying a high gate bias stress at 150 °C for 10−2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device{\textquoteright}s reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.",

keywords = "gallium nitride, HTGB, low thermal budget gate first process, ohmic contact, power device",

author = "Catherine Langpoklakpam and Liu, {An Chen} and You, {Neng Jie} and Kao, {Ming Hsuan} and Huang, {Wen Hsien} and Shen, {Chang Hong} and Jerry Tzou and Kuo, {Hao Chung} and Shieh, {Jia Min}",

note = "Publisher Copyright: {\textcopyright} 2023 by the authors.",

year = "2023",

month = mar,

doi = "10.3390/mi14030576",

language = "English",

volume = "14",

journal = "Micromachines",

issn = "2072-666X",

publisher = "Multidisciplinary Digital Publishing Institute (MDPI)",

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TY - JOUR

T1 - Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

AU - Langpoklakpam, Catherine

AU - Liu, An Chen

AU - You, Neng Jie

AU - Kao, Ming Hsuan

AU - Huang, Wen Hsien

AU - Shen, Chang Hong

AU - Tzou, Jerry

AU - Kuo, Hao Chung

AU - Shieh, Jia Min

PY - 2023/3

Y1 - 2023/3

N2 - In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from −0.85 V to −0.74 V after applying a high gate bias stress at 150 °C for 10−2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device’s reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

AB - In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from −0.85 V to −0.74 V after applying a high gate bias stress at 150 °C for 10−2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device’s reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

KW - gallium nitride

KW - HTGB

KW - low thermal budget gate first process

KW - ohmic contact

KW - power device

UR - http://www.scopus.com/inward/record.url?scp=85151645779&partnerID=8YFLogxK

U2 - 10.3390/mi14030576

DO - 10.3390/mi14030576

M3 - Article

AN - SCOPUS:85151645779

SN - 2072-666X

VL - 14

JO - Micromachines

JF - Micromachines

IS - 3

M1 - 576

ER -

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

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Keywords

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