Improving electrical performance of the scaled low-temperature poly-si thin film transistors using vacuum encapsulation technique

Wei Kai Lin; Ta Chuan Liao; Chun Yu Wu; Shih Wei Tu; Yen Ting Liu; Jun Quan Lin; Huang-Chung Cheng; Feng Tso Chien; Wan Lu Chen; Chii Wen Chen; Ya-Hsiang Tai

doi:10.1889/1.3069348

Improving electrical performance of the scaled low-temperature poly-si thin film transistors using vacuum encapsulation technique

Wei Kai Lin^*, Ta Chuan Liao, Chun Yu Wu, Shih Wei Tu, Yen Ting Liu, Jun Quan Lin, Huang-Chung Cheng, Feng Tso Chien, Wan Lu Chen, Chii Wen Chen, Ya-Hsiang Tai

^*Corresponding author for this work

Department of Photonics

Research output: Contribution to journal › Conference article › peer-review

Abstract

A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH ₄ -based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain junction.

Original language	English
Pages (from-to)	1192-1195
Number of pages	4
Journal	Digest of Technical Papers - SID International Symposium
Volume	39
Issue number	3
DOIs	https://doi.org/10.1889/1.3069348
State	Published - 30 Oct 2008
Event	2008 SID International Symposium - Los Angeles, CA, United States Duration: 20 May 2008 → 21 May 2008

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Lin, W. K., Liao, T. C., Wu, C. Y., Tu, S. W., Liu, Y. T., Lin, J. Q., Cheng, H.-C., Chien, F. T., Chen, W. L., Chen, C. W., & Tai, Y.-H. (2008). Improving electrical performance of the scaled low-temperature poly-si thin film transistors using vacuum encapsulation technique. Digest of Technical Papers - SID International Symposium, 39(3), 1192-1195. https://doi.org/10.1889/1.3069348

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title = "Improving electrical performance of the scaled low-temperature poly-si thin film transistors using vacuum encapsulation technique",

abstract = " A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH 4 -based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain junction.",

author = "Lin, {Wei Kai} and Liao, {Ta Chuan} and Wu, {Chun Yu} and Tu, {Shih Wei} and Liu, {Yen Ting} and Lin, {Jun Quan} and Huang-Chung Cheng and Chien, {Feng Tso} and Chen, {Wan Lu} and Chen, {Chii Wen} and Ya-Hsiang Tai",

year = "2008",

month = oct,

day = "30",

doi = "10.1889/1.3069348",

language = "English",

volume = "39",

pages = "1192--1195",

journal = "Digest of Technical Papers - SID International Symposium",

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T1 - Improving electrical performance of the scaled low-temperature poly-si thin film transistors using vacuum encapsulation technique

AU - Lin, Wei Kai

AU - Liao, Ta Chuan

AU - Wu, Chun Yu

AU - Tu, Shih Wei

AU - Liu, Yen Ting

AU - Lin, Jun Quan

AU - Cheng, Huang-Chung

AU - Chien, Feng Tso

AU - Chen, Wan Lu

AU - Chen, Chii Wen

AU - Tai, Ya-Hsiang

PY - 2008/10/30

Y1 - 2008/10/30

N2 - A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH 4 -based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain junction.

AB - A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH 4 -based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain junction.

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DO - 10.1889/1.3069348

M3 - Conference article

AN - SCOPUS:54549111954

SN - 0097-966X

VL - 39

SP - 1192

EP - 1195

JO - Digest of Technical Papers - SID International Symposium

JF - Digest of Technical Papers - SID International Symposium

IS - 3

T2 - 2008 SID International Symposium

Y2 - 20 May 2008 through 21 May 2008

ER -

Improving electrical performance of the scaled low-temperature poly-si thin film transistors using vacuum encapsulation technique

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