Improvement on CDM ESD robustness of high-voltage tolerant nLDMOS SCR devices by using differential doped gate

S. H. Chen, D. Linten, M. Scholz, G. Hellings, R. Boschke, G. Groeseneken, Y. C. Huang, Ming-Dou Ker

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations

    Abstract

    Early failure has been observed during CDM ESD stress on high-voltage tolerant nLDMOS-SCR devices in a standard low-voltage CMOS technology due to the gate oxide (GOX) degradation. In this work, we propose a special p+/n+ differential doped gate which boosts the CDM ESD failure current level with a factor of 3 to 9.

    Original languageEnglish
    Title of host publication2014 IEEE International Reliability Physics Symposium, IRPS 2014
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Print)9781479933167
    DOIs
    StatePublished - 1 Jan 2014
    Event52nd IEEE International Reliability Physics Symposium, IRPS 2014 - Waikoloa, HI, United States
    Duration: 1 Jun 20145 Jun 2014

    Publication series

    NameIEEE International Reliability Physics Symposium Proceedings
    ISSN (Print)1541-7026

    Conference

    Conference52nd IEEE International Reliability Physics Symposium, IRPS 2014
    Country/TerritoryUnited States
    CityWaikoloa, HI
    Period1/06/145/06/14

    Keywords

    • Electrostatic Discharge (ESD)
    • gate oxide reliability
    • high-voltage tolerant (HVT) devices
    • laterally diffused nMOS (nLDMOS)
    • transmission line pulsing (TLP) system
    • very fast TLP system (VFTLP)

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