Improved output ESD protection by dynamic gate floating design

Hun Hsien Chang, Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations


A dynamic gate floating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-μm CMOS process. Index Terms-ESD, ESD protection, output buffer.

Original languageEnglish
Pages (from-to)2076-2078
Number of pages3
JournalIEEE Transactions on Electron Devices
Issue number9
StatePublished - 1 Dec 1998


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