Improved output ESD protection by dynamic gate floating design

Hun Hsien Chang; Ming-Dou Ker

doi:10.1109/16.711378

Improved output ESD protection by dynamic gate floating design

Hun Hsien Chang, Ming-Dou Ker^*

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

A dynamic gate floating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-μm CMOS process. Index Terms-ESD, ESD protection, output buffer.

Original language	English
Pages (from-to)	2076-2078
Number of pages	3
Journal	IEEE Transactions on Electron Devices
Volume	45
Issue number	9
DOIs	https://doi.org/10.1109/16.711378
State	Published - 1 Dec 1998

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title = "Improved output ESD protection by dynamic gate floating design",

abstract = "A dynamic gate floating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-μm CMOS process. Index Terms-ESD, ESD protection, output buffer.",

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AU - Ker, Ming-Dou

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AB - A dynamic gate floating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-μm CMOS process. Index Terms-ESD, ESD protection, output buffer.

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Improved output ESD protection by dynamic gate floating design

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