Improved multi-level control of RRAM using pulse-train programming

Liang Zhao; Hong Yu Chen; Shih Chieh Wu; Zizhen Jiang; Shimeng Yu; Tuo-Hung Hou; H. S.Philip Wong; Yoshio Nishi

doi:10.1109/VLSI-TSA.2014.6839673

Improved multi-level control of RRAM using pulse-train programming

Liang Zhao, Hong Yu Chen, Shih Chieh Wu, Zizhen Jiang, Shimeng Yu, Tuo-Hung Hou, H. S.Philip Wong, Yoshio Nishi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.

Original language	English
Title of host publication	Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014
Publisher	IEEE Computer Society
Pages	1-2
Number of pages	2
ISBN (Print)	9781479922178
DOIs	https://doi.org/10.1109/VLSI-TSA.2014.6839673
State	Published - 28 Apr 2014
Event	2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014 - Hsinchu, Taiwan Duration: 28 Apr 2014 → 30 Apr 2014

Publication series

Name	Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014

Conference

Conference	2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014
Country/Territory	Taiwan
City	Hsinchu
Period	28/04/14 → 30/04/14

Access to Document

10.1109/VLSI-TSA.2014.6839673

Cite this

Zhao, L., Chen, H. Y., Wu, S. C., Jiang, Z., Yu, S., Hou, T.-H., Wong, H. S. P., & Nishi, Y. (2014). Improved multi-level control of RRAM using pulse-train programming. In Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014 (pp. 1-2). Article 6839673 (Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-TSA.2014.6839673

Zhao, Liang ; Chen, Hong Yu ; Wu, Shih Chieh et al. / Improved multi-level control of RRAM using pulse-train programming. Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014. IEEE Computer Society, 2014. pp. 1-2 (Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014).

@inproceedings{4ee04f0025e643dcbe7b4f72cdffa86f,

title = "Improved multi-level control of RRAM using pulse-train programming",

abstract = "Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.",

author = "Liang Zhao and Chen, {Hong Yu} and Wu, {Shih Chieh} and Zizhen Jiang and Shimeng Yu and Tuo-Hung Hou and Wong, {H. S.Philip} and Yoshio Nishi",

year = "2014",

month = apr,

day = "28",

doi = "10.1109/VLSI-TSA.2014.6839673",

language = "English",

isbn = "9781479922178",

series = "Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014",

publisher = "IEEE Computer Society",

pages = "1--2",

booktitle = "Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014",

address = "United States",

note = "2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014 ; Conference date: 28-04-2014 Through 30-04-2014",

}

Zhao, L, Chen, HY, Wu, SC, Jiang, Z, Yu, S, Hou, T-H, Wong, HSP & Nishi, Y 2014, Improved multi-level control of RRAM using pulse-train programming. in Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014., 6839673, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014, IEEE Computer Society, pp. 1-2, 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014, Hsinchu, Taiwan, 28/04/14. https://doi.org/10.1109/VLSI-TSA.2014.6839673

Improved multi-level control of RRAM using pulse-train programming. / Zhao, Liang; Chen, Hong Yu; Wu, Shih Chieh et al.
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014. IEEE Computer Society, 2014. p. 1-2 6839673 (Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Improved multi-level control of RRAM using pulse-train programming

AU - Zhao, Liang

AU - Chen, Hong Yu

AU - Wu, Shih Chieh

AU - Jiang, Zizhen

AU - Yu, Shimeng

AU - Hou, Tuo-Hung

AU - Wong, H. S.Philip

AU - Nishi, Yoshio

PY - 2014/4/28

Y1 - 2014/4/28

N2 - Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.

AB - Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.

UR - http://www.scopus.com/inward/record.url?scp=84904192001&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA.2014.6839673

DO - 10.1109/VLSI-TSA.2014.6839673

M3 - Conference contribution

AN - SCOPUS:84904192001

SN - 9781479922178

T3 - Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014

SP - 1

EP - 2

BT - Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014

PB - IEEE Computer Society

T2 - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014

Y2 - 28 April 2014 through 30 April 2014

ER -

Zhao L, Chen HY, Wu SC, Jiang Z, Yu S, Hou TH et al. Improved multi-level control of RRAM using pulse-train programming. In Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014. IEEE Computer Society. 2014. p. 1-2. 6839673. (Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014). doi: 10.1109/VLSI-TSA.2014.6839673

Improved multi-level control of RRAM using pulse-train programming

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