Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages

Kuan-Neng Chen; C. K. Tsang; A. W. Topol; S. H. Lee; B. K. Furraan; D. L. Rath; J. Q. Lu; A. M. Young; S. Purushothaman; W. Haensch

Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages

Kuan-Neng Chen, C. K. Tsang, A. W. Topol, S. H. Lee, B. K. Furraan, D. L. Rath, J. Q. Lu, A. M. Young, S. Purushothaman, W. Haensch

Research output: Contribution to conference › Paper › peer-review

10 Scopus citations

Abstract

In this paper we investigated the effect of Cu bonding quality on inter-level via structural reliability for 3D manufacturing applications. We developed a Cu bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO₂ CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes prove the feasibility of reliable and manufacturable 3D integrated circuits and packages.

Original language	English
Pages	195-202
Number of pages	8
State	Published - Sep 2006
Event	23rd International VLSI Multilevel Interconnection Conference, VMIC 2006 - Fremont, CA, United States Duration: 26 Sep 2006 → 28 Sep 2006

Conference

Conference	23rd International VLSI Multilevel Interconnection Conference, VMIC 2006
Country/Territory	United States
City	Fremont, CA
Period	26/09/06 → 28/09/06

Cite this

Chen, K.-N., Tsang, C. K., Topol, A. W., Lee, S. H., Furraan, B. K., Rath, D. L., Lu, J. Q., Young, A. M., Purushothaman, S., & Haensch, W. (2006). Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages. 195-202. Paper presented at 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006, Fremont, CA, United States.

@conference{67cdeac316a949fea942b34b2b8d0815,

title = "Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages",

abstract = "In this paper we investigated the effect of Cu bonding quality on inter-level via structural reliability for 3D manufacturing applications. We developed a Cu bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes prove the feasibility of reliable and manufacturable 3D integrated circuits and packages.",

author = "Kuan-Neng Chen and Tsang, {C. K.} and Topol, {A. W.} and Lee, {S. H.} and Furraan, {B. K.} and Rath, {D. L.} and Lu, {J. Q.} and Young, {A. M.} and S. Purushothaman and W. Haensch",

year = "2006",

month = sep,

language = "English",

pages = "195--202",

note = "23rd International VLSI Multilevel Interconnection Conference, VMIC 2006 ; Conference date: 26-09-2006 Through 28-09-2006",

}

Chen, K-N, Tsang, CK, Topol, AW, Lee, SH, Furraan, BK, Rath, DL, Lu, JQ, Young, AM, Purushothaman, S & Haensch, W 2006, 'Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages', Paper presented at 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006, Fremont, CA, United States, 26/09/06 - 28/09/06 pp. 195-202.

Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages. / Chen, Kuan-Neng; Tsang, C. K.; Topol, A. W. et al.
2006. 195-202 Paper presented at 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006, Fremont, CA, United States.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages

AU - Chen, Kuan-Neng

AU - Tsang, C. K.

AU - Topol, A. W.

AU - Lee, S. H.

AU - Furraan, B. K.

AU - Rath, D. L.

AU - Lu, J. Q.

AU - Young, A. M.

AU - Purushothaman, S.

AU - Haensch, W.

PY - 2006/9

Y1 - 2006/9

N2 - In this paper we investigated the effect of Cu bonding quality on inter-level via structural reliability for 3D manufacturing applications. We developed a Cu bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes prove the feasibility of reliable and manufacturable 3D integrated circuits and packages.

AB - In this paper we investigated the effect of Cu bonding quality on inter-level via structural reliability for 3D manufacturing applications. We developed a Cu bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes prove the feasibility of reliable and manufacturable 3D integrated circuits and packages.

UR - http://www.scopus.com/inward/record.url?scp=84888272824&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:84888272824

SP - 195

EP - 202

T2 - 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006

Y2 - 26 September 2006 through 28 September 2006

ER -

Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages

Abstract

Conference

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