TY - JOUR
T1 - Improved high code-rate soft bch decoder architectures with one extra error compensation
AU - Lin, Yi Min
AU - Chang, Hsie-Chia
AU - Lee, Chen-Yi
PY - 2013
Y1 - 2013
N2 - Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders.
AB - Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders.
KW - Bose-Chaudhuri-Hochquenghem (BCH) codes
KW - error-correction coding
KW - soft decoding
UR - http://www.scopus.com/inward/record.url?scp=84884900527&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2012.2227847
DO - 10.1109/TVLSI.2012.2227847
M3 - Article
AN - SCOPUS:84884900527
SN - 1063-8210
VL - 21
SP - 2160
EP - 2164
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 11
M1 - 6392304
ER -