@inproceedings{006a768c050e40a8b2ed5ff485903ad8,
title = "Improve latch-up immunity by circuit solution",
abstract = "A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively reduce the latchup trigger current that injecting into the core circuit blocks. Therefore, the latchup immunity of I-test with positive or negative trigger current applied at the I/O pins can be significantly improved.",
author = "Tsai, {Hui Wen} and Ming-Dou Ker",
year = "2015",
month = aug,
day = "25",
doi = "10.1109/IPFA.2015.7224450",
language = "English",
series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "527--530",
booktitle = "Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015",
address = "United States",
note = "null ; Conference date: 29-06-2015 Through 02-07-2015",
}