Implementation of array structured maximum likelihood decoders.

Kuei-Ann Wen; Jhing Fa Wang; Jau Yien Lee; Ming Yung Lin

doi:10.1109/ARRAYS.1988.18063

Implementation of array structured maximum likelihood decoders.

Kuei-Ann Wen^*, Jhing Fa Wang, Jau Yien Lee, Ming Yung Lin

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay-commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmissions are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.

Original language	English
Title of host publication	Proc Int Conf on Systolic Arrays
Publisher	Publ by IEEE
Pages	227-236
Number of pages	10
ISBN (Print)	0818688602
DOIs	https://doi.org/10.1109/ARRAYS.1988.18063
State	Published - 1 Dec 1988

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Name	Proc Int Conf on Systolic Arrays

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10.1109/ARRAYS.1988.18063

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title = "Implementation of array structured maximum likelihood decoders.",

abstract = "Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay-commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmissions are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.",

author = "Kuei-Ann Wen and Wang, {Jhing Fa} and Lee, {Jau Yien} and Lin, {Ming Yung}",

year = "1988",

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doi = "10.1109/ARRAYS.1988.18063",

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AU - Wen, Kuei-Ann

AU - Wang, Jhing Fa

AU - Lee, Jau Yien

AU - Lin, Ming Yung

PY - 1988/12/1

Y1 - 1988/12/1

N2 - Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay-commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmissions are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.

AB - Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay-commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmissions are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.

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DO - 10.1109/ARRAYS.1988.18063

M3 - Conference contribution

AN - SCOPUS:0024128152

SN - 0818688602

T3 - Proc Int Conf on Systolic Arrays

SP - 227

EP - 236

BT - Proc Int Conf on Systolic Arrays

PB - Publ by IEEE

ER -

Implementation of array structured maximum likelihood decoders.

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