Implementation of array structured maximum likelihood decoders.

Kuei-Ann Wen*, Jhing Fa Wang, Jau Yien Lee, Ming Yung Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay-commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmissions are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.

Original languageEnglish
Title of host publicationProc Int Conf on Systolic Arrays
PublisherPubl by IEEE
Pages227-236
Number of pages10
ISBN (Print)0818688602
DOIs
StatePublished - 1 Dec 1988

Publication series

NameProc Int Conf on Systolic Arrays

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