Implementation of a hardware-efficient EEG processor for brain monitoring systems

Chiu Kuo Chen; Ericson Chua; Shao Yen Tseng; Chih Chung Fu; Wai-Chi  Fang

doi:10.1109/SOCC.2010.5784735

Implementation of a hardware-efficient EEG processor for brain monitoring systems

Chiu Kuo Chen^*, Ericson Chua, Shao Yen Tseng, Chih Chung Fu, Wai-Chi Fang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um², up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2010
Pages	164-168
Number of pages	5
DOIs	https://doi.org/10.1109/SOCC.2010.5784735
State	Published - 1 Dec 2010
Event	23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States Duration: 27 Sep 2010 → 29 Sep 2010

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference	23rd IEEE International SOC Conference, SOCC 2010
Country/Territory	United States
City	Las Vegas, NV
Period	27/09/10 → 29/09/10

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10.1109/SOCC.2010.5784735

Cite this

@inproceedings{f3f3268abad04d83b7ae2fda07b4a023,

title = "Implementation of a hardware-efficient EEG processor for brain monitoring systems",

abstract = "This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um2, up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.",

author = "Chen, {Chiu Kuo} and Ericson Chua and Tseng, {Shao Yen} and Fu, {Chih Chung} and Wai-Chi Fang",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/SOCC.2010.5784735",

language = "English",

isbn = "9781424466832",

series = "Proceedings - IEEE International SOC Conference, SOCC 2010",

pages = "164--168",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2010",

note = "23rd IEEE International SOC Conference, SOCC 2010 ; Conference date: 27-09-2010 Through 29-09-2010",

}

Chen, CK, Chua, E, Tseng, SY, Fu, CC & Fang, W-C 2010, Implementation of a hardware-efficient EEG processor for brain monitoring systems. in Proceedings - IEEE International SOC Conference, SOCC 2010., 5784735, Proceedings - IEEE International SOC Conference, SOCC 2010, pp. 164-168, 23rd IEEE International SOC Conference, SOCC 2010, Las Vegas, NV, United States, 27/09/10. https://doi.org/10.1109/SOCC.2010.5784735

Implementation of a hardware-efficient EEG processor for brain monitoring systems. / Chen, Chiu Kuo; Chua, Ericson; Tseng, Shao Yen et al.
Proceedings - IEEE International SOC Conference, SOCC 2010. 2010. p. 164-168 5784735 (Proceedings - IEEE International SOC Conference, SOCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Implementation of a hardware-efficient EEG processor for brain monitoring systems

AU - Chen, Chiu Kuo

AU - Chua, Ericson

AU - Tseng, Shao Yen

AU - Fu, Chih Chung

AU - Fang, Wai-Chi

PY - 2010/12/1

Y1 - 2010/12/1

N2 - This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um2, up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.

AB - This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um2, up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.

UR - http://www.scopus.com/inward/record.url?scp=79960735673&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2010.5784735

DO - 10.1109/SOCC.2010.5784735

M3 - Conference contribution

AN - SCOPUS:79960735673

SN - 9781424466832

T3 - Proceedings - IEEE International SOC Conference, SOCC 2010

SP - 164

EP - 168

BT - Proceedings - IEEE International SOC Conference, SOCC 2010

T2 - 23rd IEEE International SOC Conference, SOCC 2010

Y2 - 27 September 2010 through 29 September 2010

ER -

Implementation of a hardware-efficient EEG processor for brain monitoring systems

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