Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

Po Yi Kuo; Jer Yi Lin; Tien-Sheng Chao

doi:10.1109/IEDM.2015.7409639

Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

Po Yi Kuo, Jer Yi Lin, Tien-Sheng Chao

Department of Electrophysics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (D_NW)-length (L_nw) × width (W_NW) × thickness (T_NW)-to 80nm×13nm×3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) ∼ 61 mV/dec., steep driving swing (D.S.) ∼ 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.

Original language	English
Title of host publication	2015 IEEE International Electron Devices Meeting, IEDM 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	6.3.1-6.3.4
ISBN (Electronic)	9781467398930
DOIs	https://doi.org/10.1109/IEDM.2015.7409639
State	Published - 16 Feb 2015
Event	61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States Duration: 7 Dec 2015 → 9 Dec 2015

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2016-February
ISSN (Print)	0163-1918

Conference

Conference	61st IEEE International Electron Devices Meeting, IEDM 2015
Country/Territory	United States
City	Washington
Period	7/12/15 → 9/12/15

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10.1109/IEDM.2015.7409639

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Kuo, P. Y., Lin, J. Y., & Chao, T.-S. (2015). Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing. In 2015 IEEE International Electron Devices Meeting, IEDM 2015 (pp. 6.3.1-6.3.4). Article 7409639 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409639

Kuo, Po Yi ; Lin, Jer Yi ; Chao, Tien-Sheng. / Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing. 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 6.3.1-6.3.4 (Technical Digest - International Electron Devices Meeting, IEDM).

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title = "Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing",

abstract = "The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (DNW)-length (Lnw) × width (WNW) × thickness (TNW)-to 80nm×13nm×3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) ∼ 61 mV/dec., steep driving swing (D.S.) ∼ 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.",

author = "Kuo, {Po Yi} and Lin, {Jer Yi} and Tien-Sheng Chao",

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Kuo, PY, Lin, JY & Chao, T-S 2015, Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing. in 2015 IEEE International Electron Devices Meeting, IEDM 2015., 7409639, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2016-February, Institute of Electrical and Electronics Engineers Inc., pp. 6.3.1-6.3.4, 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, United States, 7/12/15. https://doi.org/10.1109/IEDM.2015.7409639

Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing. / Kuo, Po Yi; Lin, Jer Yi; Chao, Tien-Sheng.
2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 6.3.1-6.3.4 7409639 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

AU - Kuo, Po Yi

AU - Lin, Jer Yi

AU - Chao, Tien-Sheng

PY - 2015/2/16

Y1 - 2015/2/16

N2 - The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (DNW)-length (Lnw) × width (WNW) × thickness (TNW)-to 80nm×13nm×3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) ∼ 61 mV/dec., steep driving swing (D.S.) ∼ 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.

AB - The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (DNW)-length (Lnw) × width (WNW) × thickness (TNW)-to 80nm×13nm×3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) ∼ 61 mV/dec., steep driving swing (D.S.) ∼ 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.

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Kuo PY, Lin JY, Chao TS. Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing. In 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 6.3.1-6.3.4. 7409639. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2015.7409639

Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

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