Impedance-isolation technique for ESD protection design in RF integrated circuits

Ming-Dou Ker*, Yuan Wen Hsiao

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-μm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be codesigned with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.

Original languageEnglish
Pages (from-to)341-351
Number of pages11
JournalIEICE Transactions on Electronics
VolumeE92-C
Issue number3
DOIs
StatePublished - 1 Jan 2009

Keywords

  • Electrostatic discharge (ESD)
  • Impedance-isolation technique
  • LC-tank
  • Noise figure power gain

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