Impacts of high-κ offset spacer on 65-nm node SOI devices

Ming Wen Ma; Tien-Sheng Chao; Kuo Hsing Kao; Jyun Siang Huang; Tan Fu Lei

Impacts of high-κ offset spacer on 65-nm node SOI devices

Ming Wen Ma^*, Tien-Sheng Chao, Kuo Hsing Kao, Jyun Siang Huang, Tan Fu Lei

^*Corresponding author for this work

Department of Electrophysics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I _off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the I_on/I_off current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.

Original language	English
Title of host publication	2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Pages	697-700
Number of pages	4
State	Published - May 2006
Event	2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States Duration: 7 May 2006 → 11 May 2006

Publication series

Name	2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Volume	1

Conference

Conference	2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Country/Territory	United States
City	Boston, MA
Period	7/05/06 → 11/05/06

Keywords

Fringing electric field
High-κ
Offset spacer dielectric
Silicon-on-insulator (SOI)

Cite this

@inproceedings{47c3574ffdd14fa9a427adbb5958f6bc,

title = "Impacts of high-κ offset spacer on 65-nm node SOI devices",

abstract = "In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.",

keywords = "Fringing electric field, High-κ, Offset spacer dielectric, Silicon-on-insulator (SOI)",

author = "Ma, {Ming Wen} and Tien-Sheng Chao and Kao, {Kuo Hsing} and Huang, {Jyun Siang} and Lei, {Tan Fu}",

year = "2006",

month = may,

language = "English",

isbn = "0976798565",

series = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings",

pages = "697--700",

booktitle = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings",

note = "null ; Conference date: 07-05-2006 Through 11-05-2006",

}

Ma, MW, Chao, T-S, Kao, KH, Huang, JS & Lei, TF 2006, Impacts of high-κ offset spacer on 65-nm node SOI devices. in 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings. 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings, vol. 1, pp. 697-700, 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings, Boston, MA, United States, 7/05/06.

Impacts of high-κ offset spacer on 65-nm node SOI devices. / Ma, Ming Wen; Chao, Tien-Sheng; Kao, Kuo Hsing et al.

2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings. 2006. p. 697-700 (2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Impacts of high-κ offset spacer on 65-nm node SOI devices

AU - Ma, Ming Wen

AU - Chao, Tien-Sheng

AU - Kao, Kuo Hsing

AU - Huang, Jyun Siang

AU - Lei, Tan Fu

PY - 2006/5

Y1 - 2006/5

N2 - In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.

AB - In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.

KW - Fringing electric field

KW - High-κ

KW - Offset spacer dielectric

KW - Silicon-on-insulator (SOI)

UR - http://www.scopus.com/inward/record.url?scp=33845335869&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33845335869

SN - 0976798565

SN - 9780976798569

T3 - 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings

SP - 697

EP - 700

BT - 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings

Y2 - 7 May 2006 through 11 May 2006

ER -

Impacts of high-κ offset spacer on 65-nm node SOI devices

Abstract

Publication series

Conference

Keywords

Other files and links

Fingerprint

Cite this