Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT

Ming Wang Ma; Chih Yang Chen; Chun Jung Su; Woei Cherngm Wu; Yi Hong Wu; Tsung Yu Yang; kuo Hsing Kao; Tien-Sheng Chao; Tan Fu Lei

doi:10.1109/LED.2007.914071

Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT

Ming Wang Ma^*, Chih Yang Chen, Chun Jung Su, Woei Cherngm Wu, Yi Hong Wu, Tsung Yu Yang, kuo Hsing Kao, Tien-Sheng Chao, Tan Fu Lei

^*Corresponding author for this work

Department of Electrophysics

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

In this letter, fluorine ion implantation with lowtemperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO ₂ low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine pro-file compared to that annealed at high temperature. About one order current reduction of I _min is achieved because 25% grainboundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO ₂ gate dielectric and fluorine preimplantation can simultaneously achieve low V _TH ∼ 1.32 V, excellent subthreshold swing ∼ 0.141 V/ dec, and high I _ON /Imin current ratio ∼ 1.98 × 10 ⁷ .

Original language	English
Pages (from-to)	168-170
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	29
Issue number	2
DOIs	https://doi.org/10.1109/LED.2007.914071
State	Published - 1 Feb 2008

Keywords

Fluorine implantation
High-κ hot carrier stress
Low-temperature poly-Si thin-film transistors (LTPS-TFTs)

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10.1109/LED.2007.914071

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@article{6c192084231f4a8fa239d9fe8134d14a,

title = "Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT",

abstract = " In this letter, fluorine ion implantation with lowtemperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO 2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine pro-file compared to that annealed at high temperature. About one order current reduction of I min is achieved because 25% grainboundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO 2 gate dielectric and fluorine preimplantation can simultaneously achieve low V TH ∼ 1.32 V, excellent subthreshold swing ∼ 0.141 V/ dec, and high I ON /Imin current ratio ∼ 1.98 × 10 7 .",

keywords = "Fluorine implantation, High-κ hot carrier stress, Low-temperature poly-Si thin-film transistors (LTPS-TFTs)",

author = "Ma, {Ming Wang} and Chen, {Chih Yang} and Su, {Chun Jung} and Wu, {Woei Cherngm} and Wu, {Yi Hong} and Yang, {Tsung Yu} and Kao, {kuo Hsing} and Tien-Sheng Chao and Lei, {Tan Fu}",

year = "2008",

month = feb,

day = "1",

doi = "10.1109/LED.2007.914071",

language = "English",

volume = "29",

pages = "168--170",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

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TY - JOUR

T1 - Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT

AU - Ma, Ming Wang

AU - Chen, Chih Yang

AU - Su, Chun Jung

AU - Wu, Woei Cherngm

AU - Wu, Yi Hong

AU - Yang, Tsung Yu

AU - Kao, kuo Hsing

AU - Chao, Tien-Sheng

AU - Lei, Tan Fu

PY - 2008/2/1

Y1 - 2008/2/1

N2 - In this letter, fluorine ion implantation with lowtemperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO 2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine pro-file compared to that annealed at high temperature. About one order current reduction of I min is achieved because 25% grainboundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO 2 gate dielectric and fluorine preimplantation can simultaneously achieve low V TH ∼ 1.32 V, excellent subthreshold swing ∼ 0.141 V/ dec, and high I ON /Imin current ratio ∼ 1.98 × 10 7 .

AB - In this letter, fluorine ion implantation with lowtemperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO 2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine pro-file compared to that annealed at high temperature. About one order current reduction of I min is achieved because 25% grainboundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO 2 gate dielectric and fluorine preimplantation can simultaneously achieve low V TH ∼ 1.32 V, excellent subthreshold swing ∼ 0.141 V/ dec, and high I ON /Imin current ratio ∼ 1.98 × 10 7 .

KW - Fluorine implantation

KW - High-κ hot carrier stress

KW - Low-temperature poly-Si thin-film transistors (LTPS-TFTs)

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U2 - 10.1109/LED.2007.914071

DO - 10.1109/LED.2007.914071

M3 - Article

AN - SCOPUS:39649102335

SN - 0741-3106

VL - 29

SP - 168

EP - 170

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 2

ER -

Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT

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Keywords

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