Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Ming-Dou Ker; Chun Yu Lin; Chang Tang-Long Chang

doi:10.1109/IRPS.2011.5784565

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Ming-Dou Ker^*, Chun Yu Lin, Chang Tang-Long Chang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

Original language	English
Title of host publication	2011 International Reliability Physics Symposium, IRPS 2011
DOIs	https://doi.org/10.1109/IRPS.2011.5784565
State	Published - 23 Jun 2011
Event	49th International Reliability Physics Symposium, IRPS 2011 - Monterey, CA, United States Duration: 10 Apr 2011 → 14 Apr 2011

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Conference

Conference	49th International Reliability Physics Symposium, IRPS 2011
Country/Territory	United States
City	Monterey, CA
Period	10/04/11 → 14/04/11

Keywords

Charged-device model (CDM)
ESD
shielding line

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10.1109/IRPS.2011.5784565

Cite this

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title = "Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process",

abstract = "The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.",

keywords = "Charged-device model (CDM), ESD, shielding line",

author = "Ming-Dou Ker and Lin, {Chun Yu} and {Tang-Long Chang}, Chang",

year = "2011",

month = jun,

day = "23",

doi = "10.1109/IRPS.2011.5784565",

language = "English",

isbn = "9781424491117",

series = "IEEE International Reliability Physics Symposium Proceedings",

booktitle = "2011 International Reliability Physics Symposium, IRPS 2011",

note = "49th International Reliability Physics Symposium, IRPS 2011 ; Conference date: 10-04-2011 Through 14-04-2011",

}

Ker, M-D, Lin, CY & Tang-Long Chang, C 2011, Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. in 2011 International Reliability Physics Symposium, IRPS 2011., 5784565, IEEE International Reliability Physics Symposium Proceedings, 49th International Reliability Physics Symposium, IRPS 2011, Monterey, CA, United States, 10/04/11. https://doi.org/10.1109/IRPS.2011.5784565

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. / Ker, Ming-Dou; Lin, Chun Yu; Tang-Long Chang, Chang.
2011 International Reliability Physics Symposium, IRPS 2011. 2011. 5784565 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

AU - Ker, Ming-Dou

AU - Lin, Chun Yu

AU - Tang-Long Chang, Chang

PY - 2011/6/23

Y1 - 2011/6/23

N2 - The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

AB - The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

KW - Charged-device model (CDM)

KW - ESD

KW - shielding line

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SN - 9781424491117

T3 - IEEE International Reliability Physics Symposium Proceedings

BT - 2011 International Reliability Physics Symposium, IRPS 2011

T2 - 49th International Reliability Physics Symposium, IRPS 2011

Y2 - 10 April 2011 through 14 April 2011

ER -

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

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