Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

Seian Feng Liao, Kai Neng Tang, Ming-Dou Ker, Jia Rong Yeh, Hwa Chyi Chiou, Yeh Jen Huang, Chun Chien Tsai, Yeh Ning Jou, Geeng Lih Lin

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations

    Fingerprint

    Dive into the research topics of 'Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection'. Together they form a unique fingerprint.

    Engineering & Materials Science