Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

Seian Feng Liao; Kai Neng Tang; Ming-Dou Ker; Jia Rong Yeh; Hwa Chyi Chiou; Yeh Jen Huang; Chun Chien Tsai; Yeh Ning Jou; Geeng Lih Lin

doi:10.1109/ECCTD.2015.7300108

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

Seian Feng Liao, Kai Neng Tang, Ming-Dou Ker, Jia Rong Yeh, Hwa Chyi Chiou, Yeh Jen Huang, Chun Chien Tsai, Yeh Ning Jou, Geeng Lih Lin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

Original language	English
Title of host publication	2015 European Conference on Circuit Theory and Design, ECCTD 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479998777
DOIs	https://doi.org/10.1109/ECCTD.2015.7300108
State	Published - 16 Oct 2015
Event	European Conference on Circuit Theory and Design, ECCTD 2015 - Trondheim, Norway Duration: 24 Aug 2015 → 26 Aug 2015

Publication series

Name	2015 European Conference on Circuit Theory and Design, ECCTD 2015

Conference

Conference	European Conference on Circuit Theory and Design, ECCTD 2015
Country/Territory	Norway
City	Trondheim
Period	24/08/15 → 26/08/15

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10.1109/ECCTD.2015.7300108

Cite this

Liao, S. F., Tang, K. N., Ker, M-D., Yeh, J. R., Chiou, H. C., Huang, Y. J., Tsai, C. C., Jou, Y. N., & Lin, G. L. (2015). Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. In 2015 European Conference on Circuit Theory and Design, ECCTD 2015 [7300108] (2015 European Conference on Circuit Theory and Design, ECCTD 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECCTD.2015.7300108

@inproceedings{6241db4806a546a1b510e65c1648281c,

title = "Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection",

abstract = "Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.",

author = "Liao, {Seian Feng} and Tang, {Kai Neng} and Ming-Dou Ker and Yeh, {Jia Rong} and Chiou, {Hwa Chyi} and Huang, {Yeh Jen} and Tsai, {Chun Chien} and Jou, {Yeh Ning} and Lin, {Geeng Lih}",

year = "2015",

month = oct,

day = "16",

doi = "10.1109/ECCTD.2015.7300108",

language = "English",

series = "2015 European Conference on Circuit Theory and Design, ECCTD 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 European Conference on Circuit Theory and Design, ECCTD 2015",

address = "United States",

note = "null ; Conference date: 24-08-2015 Through 26-08-2015",

}

Liao, SF, Tang, KN, Ker, M-D, Yeh, JR, Chiou, HC, Huang, YJ, Tsai, CC, Jou, YN & Lin, GL 2015, Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. in 2015 European Conference on Circuit Theory and Design, ECCTD 2015., 7300108, 2015 European Conference on Circuit Theory and Design, ECCTD 2015, Institute of Electrical and Electronics Engineers Inc., European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, 24/08/15. https://doi.org/10.1109/ECCTD.2015.7300108

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. / Liao, Seian Feng; Tang, Kai Neng; Ker, Ming-Dou et al.

2015 European Conference on Circuit Theory and Design, ECCTD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7300108 (2015 European Conference on Circuit Theory and Design, ECCTD 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

AU - Liao, Seian Feng

AU - Tang, Kai Neng

AU - Ker, Ming-Dou

AU - Yeh, Jia Rong

AU - Chiou, Hwa Chyi

AU - Huang, Yeh Jen

AU - Tsai, Chun Chien

AU - Jou, Yeh Ning

AU - Lin, Geeng Lih

PY - 2015/10/16

Y1 - 2015/10/16

N2 - Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

AB - Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

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U2 - 10.1109/ECCTD.2015.7300108

DO - 10.1109/ECCTD.2015.7300108

M3 - Conference contribution

AN - SCOPUS:84959516661

T3 - 2015 European Conference on Circuit Theory and Design, ECCTD 2015

BT - 2015 European Conference on Circuit Theory and Design, ECCTD 2015

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 24 August 2015 through 26 August 2015

ER -

Liao SF, Tang KN, Ker M-D, Yeh JR, Chiou HC, Huang YJ et al. Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. In 2015 European Conference on Circuit Theory and Design, ECCTD 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7300108. (2015 European Conference on Circuit Theory and Design, ECCTD 2015). doi: 10.1109/ECCTD.2015.7300108

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

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