TY - GEN
T1 - Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology
AU - Chen, Jung Sheng
AU - Ker, Ming-Dou
PY - 2007
Y1 - 2007
N2 - The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.
AB - The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.
UR - http://www.scopus.com/inward/record.url?scp=34548781895&partnerID=8YFLogxK
U2 - 10.1109/RELPHY.2007.370002
DO - 10.1109/RELPHY.2007.370002
M3 - Conference contribution
AN - SCOPUS:34548781895
SN - 1424409195
SN - 9781424409198
T3 - Annual Proceedings - Reliability Physics (Symposium)
SP - 664
EP - 665
BT - 2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
T2 - 45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
Y2 - 15 April 2007 through 19 April 2007
ER -