Impact of charge trapping effect on negative bias temperature instability in P-MOSFETs with HfO₂/SiON gate stack

In our study, we systematically investigated the behavior of charge trapping in P-MOSFETs with HfO₂/SiON gate stack. We found that typical linear extrapolation does not work well for the lifetime extraction at normal operation condition since the polarity of dominant trapped charge in high-k dielectric is not the same at lower and higher stress voltage regimes. This phenomenon is considered the competition of hole trapping and electron trapping with respect to applied gate voltages. Besides, the results of AC stress reveal the distinct responses to electrons and holes. It indicates that electrons can easily follow the AC signal while holes seem to need more time for the response at AC stress.