Impact of back gate bias on hot-carrier effects of n-channel Tri-Gate FETs (TGFETs)

Chia Pin Lin*, Bing-Yue Tsui

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations

    Abstract

    The hot-carrier effects of non-planar tri-gate SOI FET (TGFET) with back-gate bias were investigated. Negative back gate bias could raise the influence of buried oxide defects and then degrade the device quickly. For TGFETs with ultra-narrow fin width and side gate extension, the smaller buried oxide interface area and more obvious screening effect terminate the field lines to obviate the back gate bias efficiently. The extrapolated hot-carrier lifetime encourages the TGFETs as promising sub-10nm devices.

    Original languageEnglish
    Title of host publication2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
    Pages82-83
    Number of pages2
    DOIs
    StatePublished - 1 Dec 2006
    Event2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Hsinchu, Taiwan
    Duration: 24 Apr 200626 Apr 2006

    Publication series

    NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

    Conference

    Conference2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
    Country/TerritoryTaiwan
    CityHsinchu
    Period24/04/0626/04/06

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