In this paper, the lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered on by noise pulses when the IC's are in the normal operating condition. A cascode design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS IC's without causing unexpected operation errors or latchup danger. Such cascoded LVTSCR's with a holding voltage greater than VDD of an IC can provide CMOS IC's with effective component-level ESD protection but without being accidentally triggered on by system-level overshooting or undershooting noise pulses.
|Number of pages||14|
|Journal||Electrical Overstress/Electrostatic Discharge Symposium Proceedings|
|State||Published - 1 Dec 1998|
|Event||Proceedings of the 1998 20th Annual International EOS/ESD Symposium - Reno, NV, USA|
Duration: 6 Oct 1998 → 8 Oct 1998