High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric

Bing Yue Tsui*, Chia Lung Hung, Ya Ru Jhuang, Yi Ting Huang, Jung Chien Cheng, Fang Hsin Lu, Yi Ting Shih, Ya Hsin Lee, Liang Yu Chen, Fu Hsiang Chuang, Pei Wen Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

We report a high performance 4H-SiC CMOS process for sub-10 V operation featuring LOCal Oxidation of SiC isolation and balanced gate oxidation process. Temperature stability of SiC MOSFETs and CMOS inverters are characterized up to 300 °C. High voltage gain of 62 V/V and 13 V/V at room temperature and 300 °C, respectively, are demonstrated. The proposed process technology is promising for SiC power system-on-a-chip.

Original languageEnglish
Title of host publicationVLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665419345
DOIs
StatePublished - 19 Apr 2021
Event2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021 - Hsinchu, Taiwan
Duration: 19 Apr 202122 Apr 2021

Publication series

NameVLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings

Conference

Conference2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021
Country/TerritoryTaiwan
CityHsinchu
Period19/04/2122/04/21

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