High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric

Bing Yue Tsui; Chia Lung Hung; Ya Ru Jhuang; Yi Ting Huang; Jung Chien Cheng; Fang Hsin Lu; Yi Ting Shih; Ya Hsin Lee; Liang Yu Chen; Fu Hsiang Chuang; Pei Wen Li

doi:10.1109/VLSI-TSA51926.2021.9440126

High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric

Bing Yue Tsui^*, Chia Lung Hung, Ya Ru Jhuang, Yi Ting Huang, Jung Chien Cheng, Fang Hsin Lu, Yi Ting Shih, Ya Hsin Lee, Liang Yu Chen, Fu Hsiang Chuang, Pei Wen Li

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We report a high performance 4H-SiC CMOS process for sub-10 V operation featuring LOCal Oxidation of SiC isolation and balanced gate oxidation process. Temperature stability of SiC MOSFETs and CMOS inverters are characterized up to 300 °C. High voltage gain of 62 V/V and 13 V/V at room temperature and 300 °C, respectively, are demonstrated. The proposed process technology is promising for SiC power system-on-a-chip.

Original language	English
Title of host publication	VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665419345
DOIs	https://doi.org/10.1109/VLSI-TSA51926.2021.9440126
State	Published - 19 Apr 2021
Event	2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021 - Hsinchu, Taiwan Duration: 19 Apr 2021 → 22 Apr 2021

Publication series

Name	VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings

Conference

Conference	2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021
Country/Territory	Taiwan
City	Hsinchu
Period	19/04/21 → 22/04/21

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10.1109/VLSI-TSA51926.2021.9440126

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Tsui, B. Y., Hung, C. L., Jhuang, Y. R., Huang, Y. T., Cheng, J. C., Lu, F. H., Shih, Y. T., Lee, Y. H., Chen, L. Y., Chuang, F. H., & Li, P. W. (2021). High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric. In VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings [9440126] (VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA51926.2021.9440126

Tsui, Bing Yue ; Hung, Chia Lung ; Jhuang, Ya Ru ; Huang, Yi Ting ; Cheng, Jung Chien ; Lu, Fang Hsin ; Shih, Yi Ting ; Lee, Ya Hsin ; Chen, Liang Yu ; Chuang, Fu Hsiang ; Li, Pei Wen. / High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric. VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. (VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings).

@inproceedings{e1336011894d4579b2d4fbcc6497ec6a,

title = "High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric",

abstract = "We report a high performance 4H-SiC CMOS process for sub-10 V operation featuring LOCal Oxidation of SiC isolation and balanced gate oxidation process. Temperature stability of SiC MOSFETs and CMOS inverters are characterized up to 300 °C. High voltage gain of 62 V/V and 13 V/V at room temperature and 300 °C, respectively, are demonstrated. The proposed process technology is promising for SiC power system-on-a-chip. ",

author = "Tsui, {Bing Yue} and Hung, {Chia Lung} and Jhuang, {Ya Ru} and Huang, {Yi Ting} and Cheng, {Jung Chien} and Lu, {Fang Hsin} and Shih, {Yi Ting} and Lee, {Ya Hsin} and Chen, {Liang Yu} and Chuang, {Fu Hsiang} and Li, {Pei Wen}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; null ; Conference date: 19-04-2021 Through 22-04-2021",

year = "2021",

month = apr,

day = "19",

doi = "10.1109/VLSI-TSA51926.2021.9440126",

language = "English",

series = "VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings",

address = "United States",

}

Tsui, BY, Hung, CL, Jhuang, YR, Huang, YT, Cheng, JC, Lu, FH, Shih, YT, Lee, YH, Chen, LY, Chuang, FH & Li, PW 2021, High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric. in VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings., 9440126, VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings, Institute of Electrical and Electronics Engineers Inc., 2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021, Hsinchu, Taiwan, 19/04/21. https://doi.org/10.1109/VLSI-TSA51926.2021.9440126

High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric. / Tsui, Bing Yue; Hung, Chia Lung; Jhuang, Ya Ru; Huang, Yi Ting; Cheng, Jung Chien; Lu, Fang Hsin; Shih, Yi Ting; Lee, Ya Hsin; Chen, Liang Yu; Chuang, Fu Hsiang; Li, Pei Wen.

VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9440126 (VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric

AU - Tsui, Bing Yue

AU - Hung, Chia Lung

AU - Jhuang, Ya Ru

AU - Huang, Yi Ting

AU - Cheng, Jung Chien

AU - Lu, Fang Hsin

AU - Shih, Yi Ting

AU - Lee, Ya Hsin

AU - Chen, Liang Yu

AU - Chuang, Fu Hsiang

AU - Li, Pei Wen

PY - 2021/4/19

Y1 - 2021/4/19

N2 - We report a high performance 4H-SiC CMOS process for sub-10 V operation featuring LOCal Oxidation of SiC isolation and balanced gate oxidation process. Temperature stability of SiC MOSFETs and CMOS inverters are characterized up to 300 °C. High voltage gain of 62 V/V and 13 V/V at room temperature and 300 °C, respectively, are demonstrated. The proposed process technology is promising for SiC power system-on-a-chip.

AB - We report a high performance 4H-SiC CMOS process for sub-10 V operation featuring LOCal Oxidation of SiC isolation and balanced gate oxidation process. Temperature stability of SiC MOSFETs and CMOS inverters are characterized up to 300 °C. High voltage gain of 62 V/V and 13 V/V at room temperature and 300 °C, respectively, are demonstrated. The proposed process technology is promising for SiC power system-on-a-chip.

UR - http://www.scopus.com/inward/record.url?scp=85108165185&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA51926.2021.9440126

DO - 10.1109/VLSI-TSA51926.2021.9440126

M3 - Conference contribution

AN - SCOPUS:85108165185

T3 - VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings

BT - VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 19 April 2021 through 22 April 2021

ER -

Tsui BY, Hung CL, Jhuang YR, Huang YT, Cheng JC, Lu FH et al. High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric. In VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9440126. (VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings). https://doi.org/10.1109/VLSI-TSA51926.2021.9440126

High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric

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