On-chip high-voltage (HV) power management integrated circuits would deliver smaller form factor, lower system cost, higher power efficiency, and suppressed noise in system-on-chip designs. A reliable HV amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology has been presented for potential applications of monolithic 3-D integration on CMOS. By using a process temperature below 200 °C, the instability of positive- and negative-bias stresses can be carefully minimized. The HV a-IGZO TFT with an Al2O3 high-k gate dielectric possesses a high breakdown voltage exceeding 45 V, a high saturation mobility of 11.3 cm2/Vs, and a large ON-/OFF-current ratio of 109. The long-term reliability study projects that the device can be operated at 20 V for ten years without catastrophic dielectric breakdown while maintaining sufficient ON-current.
- 3-D integration
- amorphous-indium-gallium-zinc-oxide (a-IGZO)
- high-k dielectric
- power management IC (PMIC)
- thin-film transistor (TFT)