TY - JOUR
T1 - High-Temperature TDDB Investigation on High Performance-Centered Hybrid HZO/HfON/Al2O3, Ferro-Electric Charge-Trap (FEG) GaN-HEMT
AU - Rathaur, Shivendra K.
AU - Wu, Jui Sheng
AU - Yang, Tsung Ying
AU - Amin, Asifa
AU - Dixit, Abhisek
AU - Chang, Edward Yi
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2023/9/1
Y1 - 2023/9/1
N2 - This article investigates a hybrid ferroelectric charge trap (HFCT)-based HfZrO4/HfOXNY/ Al2O3/AlGaN/GaN gate-stack under constant positive gate voltage stress over time and temperature variability. The experimentally characterized breakdown (BD) analysis implies a thermally assisted tunneling (TAT) BD owing to the negative temperature coefficient of BD voltage. Moreover, the step gate stress depicts a relatively lower BD voltage of 20 V compared to the linear gate stress voltage of 21.85 V attributed to performance degradation due to stress. In addition, the Weibull distribution, which validates the intrinsic degradation of the gate-stack, is used to estimate its lifetime. An operating voltage of 7.41 V exhibits a ten-year lifetime at 150 °C extrapolated over multiple stress conditions. Furthermore, the activation energy from 0.63 to 0.67 eV validates deep-level E3 traps within the GaN barrier layer and the trapping of electrons during degradation, thus, revealing the point-level defect generation leading to the time-dependent gate dielectric BD (TDDB). The robustness and superior reliability of the HFCT gate-stack are recognized, and the single degradation mechanism contributes to the final device failure in the TDDB test.
AB - This article investigates a hybrid ferroelectric charge trap (HFCT)-based HfZrO4/HfOXNY/ Al2O3/AlGaN/GaN gate-stack under constant positive gate voltage stress over time and temperature variability. The experimentally characterized breakdown (BD) analysis implies a thermally assisted tunneling (TAT) BD owing to the negative temperature coefficient of BD voltage. Moreover, the step gate stress depicts a relatively lower BD voltage of 20 V compared to the linear gate stress voltage of 21.85 V attributed to performance degradation due to stress. In addition, the Weibull distribution, which validates the intrinsic degradation of the gate-stack, is used to estimate its lifetime. An operating voltage of 7.41 V exhibits a ten-year lifetime at 150 °C extrapolated over multiple stress conditions. Furthermore, the activation energy from 0.63 to 0.67 eV validates deep-level E3 traps within the GaN barrier layer and the trapping of electrons during degradation, thus, revealing the point-level defect generation leading to the time-dependent gate dielectric BD (TDDB). The robustness and superior reliability of the HFCT gate-stack are recognized, and the single degradation mechanism contributes to the final device failure in the TDDB test.
KW - Dielectric reliability
KW - hard breakdown (HBD)
KW - mean time to failure (MTTF)
KW - metal-insulator-semiconductor (MIS)-high-electron mobility transistor (HEMT)
KW - time-dependent gate dielectric breakdown (TDDB)
KW - Weibull statistics
UR - http://www.scopus.com/inward/record.url?scp=85165873093&partnerID=8YFLogxK
U2 - 10.1109/TED.2023.3295766
DO - 10.1109/TED.2023.3295766
M3 - Article
AN - SCOPUS:85165873093
SN - 0018-9383
VL - 70
SP - 4584
EP - 4590
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 9
ER -