High Speed Negative Capacitance Ferroelectric Memory

Chun-Yen Chang, Chia Chi Fan, Chien Liu, Yu Chien Chiu, Chun-Hu Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.
Original languageEnglish
Title of host publication12th IEEE International Conference on ASIC (ASICON)
StatePublished - 2017


Dive into the research topics of 'High Speed Negative Capacitance Ferroelectric Memory'. Together they form a unique fingerprint.

Cite this