High-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors

Joseph D. George; Jerome D. Harr; Rock Young; Gerry T. Watanabe; Carl J. Anderson; Young H. Kwark; Harris F. Basit; Shushau Fang; Keh chung Wang; Peter M. Asbeck; Mau-Chung Chang; Randy Nubling; Gerald J. Sullivan; Mark McDonald; Chuck Honaker; Tom McDermott

doi:10.1109/ISSCC.1989.48253

High-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors

Joseph D. George^*, Jerome D. Harr, Rock Young, Gerry T. Watanabe, Carl J. Anderson, Young H. Kwark, Harris F. Basit, Shushau Fang, Keh chung Wang, Peter M. Asbeck, Mau-Chung Chang, Randy Nubling, Gerald J. Sullivan, Mark McDonald, Chuck Honaker, Tom McDermott

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have f_t values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.

Original language	English
Pages (from-to)	186-187, 336
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	32
DOIs	https://doi.org/10.1109/ISSCC.1989.48253
State	Published - 1 Dec 1989
Event	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA Duration: 15 Feb 1989 → 17 Feb 1989

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George, J. D., Harr, J. D., Young, R., Watanabe, G. T., Anderson, C. J., Kwark, Y. H., Basit, H. F., Fang, S., Wang, K. C., Asbeck, P. M., Chang, M-C., Nubling, R., Sullivan, G. J., McDonald, M., Honaker, C., & McDermott, T. (1989). High-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 32, 186-187, 336. https://doi.org/10.1109/ISSCC.1989.48253

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title = "High-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors",

abstract = "The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have ft values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.",

author = "George, {Joseph D.} and Harr, {Jerome D.} and Rock Young and Watanabe, {Gerry T.} and Anderson, {Carl J.} and Kwark, {Young H.} and Basit, {Harris F.} and Shushau Fang and Wang, {Keh chung} and Asbeck, {Peter M.} and Mau-Chung Chang and Randy Nubling and Sullivan, {Gerald J.} and Mark McDonald and Chuck Honaker and Tom McDermott",

year = "1989",

month = dec,

day = "1",

doi = "10.1109/ISSCC.1989.48253",

language = "English",

volume = "32",

pages = "186--187, 336",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 15-02-1989 Through 17-02-1989",

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George, JD, Harr, JD, Young, R, Watanabe, GT, Anderson, CJ, Kwark, YH, Basit, HF, Fang, S, Wang, KC, Asbeck, PM, Chang, M-C, Nubling, R, Sullivan, GJ, McDonald, M, Honaker, C & McDermott, T 1989, 'High-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors', Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 32, pp. 186-187, 336. https://doi.org/10.1109/ISSCC.1989.48253

TY - JOUR

T1 - High-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors

AU - George, Joseph D.

AU - Harr, Jerome D.

AU - Young, Rock

AU - Watanabe, Gerry T.

AU - Anderson, Carl J.

AU - Kwark, Young H.

AU - Basit, Harris F.

AU - Fang, Shushau

AU - Wang, Keh chung

AU - Asbeck, Peter M.

AU - Chang, Mau-Chung

AU - Nubling, Randy

AU - Sullivan, Gerald J.

AU - McDonald, Mark

AU - Honaker, Chuck

AU - McDermott, Tom

PY - 1989/12/1

Y1 - 1989/12/1

N2 - The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have ft values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.

AB - The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have ft values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.

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U2 - 10.1109/ISSCC.1989.48253

DO - 10.1109/ISSCC.1989.48253

M3 - Conference article

AN - SCOPUS:0024939062

VL - 32

SP - 186-187, 336

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

Y2 - 15 February 1989 through 17 February 1989

ER -

High-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors

Abstract

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