High-speed digital comb filter for ΣΔ analog-to-digital conversion

Louis Luh; John Choma; Jeffrey Draper; Her-Ming Chiueh

High-speed digital comb filter for ΣΔ analog-to-digital conversion

Louis Luh^*, John Choma, Jeffrey Draper, Her-Ming Chiueh

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

5 Scopus citations

Abstract

A new approach for implementing a digital decimator for high-speed ΣΔ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2μm standard CMOS process. With a single 5V power supply, this filter can operate at a frequency up to 115MHz. The power consumption is about 35mW and the active area is 1083 × 965 μm².

Original language	English
Pages	356-359
Number of pages	4
State	Published - 1 Dec 1999
Event	1999 IEEE 42nd Midwest Symposium on Circuits and Sistems - Las Cruces, NM, USA Duration: 8 Aug 1999 → 11 Aug 1999

Conference

Conference	1999 IEEE 42nd Midwest Symposium on Circuits and Sistems
City	Las Cruces, NM, USA
Period	8/08/99 → 11/08/99

Cite this

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title = "High-speed digital comb filter for ΣΔ analog-to-digital conversion",

abstract = "A new approach for implementing a digital decimator for high-speed ΣΔ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2μm standard CMOS process. With a single 5V power supply, this filter can operate at a frequency up to 115MHz. The power consumption is about 35mW and the active area is 1083 × 965 μm2.",

author = "Louis Luh and John Choma and Jeffrey Draper and Her-Ming Chiueh",

year = "1999",

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note = "1999 IEEE 42nd Midwest Symposium on Circuits and Sistems ; Conference date: 08-08-1999 Through 11-08-1999",

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T1 - High-speed digital comb filter for ΣΔ analog-to-digital conversion

AU - Luh, Louis

AU - Choma, John

AU - Draper, Jeffrey

AU - Chiueh, Her-Ming

PY - 1999/12/1

Y1 - 1999/12/1

N2 - A new approach for implementing a digital decimator for high-speed ΣΔ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2μm standard CMOS process. With a single 5V power supply, this filter can operate at a frequency up to 115MHz. The power consumption is about 35mW and the active area is 1083 × 965 μm2.

AB - A new approach for implementing a digital decimator for high-speed ΣΔ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2μm standard CMOS process. With a single 5V power supply, this filter can operate at a frequency up to 115MHz. The power consumption is about 35mW and the active area is 1083 × 965 μm2.

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M3 - Paper

AN - SCOPUS:0033292270

SP - 356

EP - 359

T2 - 1999 IEEE 42nd Midwest Symposium on Circuits and Sistems

Y2 - 8 August 1999 through 11 August 1999

ER -

High-speed digital comb filter for ΣΔ analog-to-digital conversion

Abstract

Conference

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