High-speed area-efficient recursive DFT/IDFT architectures

Lan-Da Van*, Chih Chyau Yang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

15 Scopus citations


In this paper, we propose several high-speed area-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) designs adopting the module-sharing and register-splitting schemes. The proposed core architecture achieves one multiplier reduction as well as less critical period and a saving of nearly half multiplications compared with the second-order and first-order recursive DFT structures, respectively. So as to reduce the number of computation cycles, based on the new core design, we develop the area-efficient parallel and folded recursive DFT/IDFT architectures. Moreover, due to the advantages of regular and modular structure, the resulting high-speed area-efficient recursive DFT/IDFT architectures are amenable to application-specific integrated circuit (ASIC) design.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 7 Sep 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004


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