High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Tai Hsiang Lai; Ming-Dou Ker; Wei Jen Chang; Tien Hao Tang; Kuan Cheng Su

doi:10.1109/RELPHY.2008.4558959

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Tai Hsiang Lai^*, Ming-Dou Ker, Wei Jen Chang, Tien Hao Tang, Kuan Cheng Su

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.

Original language	English
Title of host publication	46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS
Pages	627-628
Number of pages	2
DOIs	https://doi.org/10.1109/RELPHY.2008.4558959
State	Published - 17 Sep 2008
Event	46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS - Phoenix, AZ, United States Duration: 27 Apr 2008 → 1 May 2008

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Conference

Conference	46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS
Country/Territory	United States
City	Phoenix, AZ
Period	27/04/08 → 1/05/08

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10.1109/RELPHY.2008.4558959

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Lai, T. H., Ker, M-D., Chang, W. J., Tang, T. H., & Su, K. C. (2008). High-robust ESD protection structure with embedded SCR in high-voltage CMOS process. In 46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS (pp. 627-628). [4558959] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/RELPHY.2008.4558959

@inproceedings{dc5601e6db3d4397832332311847f769,

title = "High-robust ESD protection structure with embedded SCR in high-voltage CMOS process",

abstract = "The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.",

author = "Lai, {Tai Hsiang} and Ming-Dou Ker and Chang, {Wei Jen} and Tang, {Tien Hao} and Su, {Kuan Cheng}",

year = "2008",

month = sep,

day = "17",

doi = "10.1109/RELPHY.2008.4558959",

language = "English",

isbn = "9781424420506",

series = "IEEE International Reliability Physics Symposium Proceedings",

pages = "627--628",

booktitle = "46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS",

note = "46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS ; Conference date: 27-04-2008 Through 01-05-2008",

}

Lai, TH, Ker, M-D, Chang, WJ, Tang, TH & Su, KC 2008, High-robust ESD protection structure with embedded SCR in high-voltage CMOS process. in 46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS., 4558959, IEEE International Reliability Physics Symposium Proceedings, pp. 627-628, 46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS, Phoenix, AZ, United States, 27/04/08. https://doi.org/10.1109/RELPHY.2008.4558959

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process. / Lai, Tai Hsiang; Ker, Ming-Dou; Chang, Wei Jen et al.
46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS. 2008. p. 627-628 4558959 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

AU - Lai, Tai Hsiang

AU - Ker, Ming-Dou

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AU - Tang, Tien Hao

AU - Su, Kuan Cheng

PY - 2008/9/17

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N2 - The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.

AB - The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.

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SN - 9781424420506

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T2 - 46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS

Y2 - 27 April 2008 through 1 May 2008

ER -

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

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