High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Tai Hsiang Lai*, Ming-Dou Ker, Wei Jen Chang, Tien Hao Tang, Kuan Cheng Su

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    9 Scopus citations

    Abstract

    The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.

    Original languageEnglish
    Title of host publication46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS
    Pages627-628
    Number of pages2
    DOIs
    StatePublished - 2008
    Event46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS - Phoenix, AZ, United States
    Duration: 27 Apr 20081 May 2008

    Publication series

    NameIEEE International Reliability Physics Symposium Proceedings
    ISSN (Print)1541-7026

    Conference

    Conference46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS
    Country/TerritoryUnited States
    CityPhoenix, AZ
    Period27/04/081/05/08

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