High performance RF characteristics of raised gate/source/drain CMOS with Co salicide

T. Ohguro*, H. Naruse, H. Sugaya, S. Nakamura, E. Morifuji, H. Kimijima, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

27 Scopus citations


In order to obtain high performance analog MOSFET, it is important to reduce gate resistance. Recently W/TiN, CoSi2 and NiSi gate electrodes are proposed to realize these requirements. Especially, Co salicided T-shape gate electrode is easy to realize low gate resistance below 1.5 ohm/sq. with a small number increase of process steps. Additionally, short channel effects are improved because the junction depth from Si substrate surface at deeper source and drain regions become shallower due to raised source and drain. In this paper, we demonstrate an excellent analog characteristics of Co salicided T-shape gate RF CMOS technology making use of a raised gate/source/drain structures. Extremely high fmax value of 70 GHz was realized by 0.10 μm gate length nMOSFET with low noise and low power consumption.

Original languageEnglish
Pages (from-to)136-137
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 1998
EventProceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 9 Jun 199811 Jun 1998


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