High performance of Ge nMOSFETs Using SiO2 interfacial layer and TiLaO gate dielectric

W. B. Chen; Albert Chin

doi:10.1109/LED.2009.2035719

High performance of Ge nMOSFETs Using SiO₂ interfacial layer and TiLaO gate dielectric

W. B. Chen, Albert Chin

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

Using a SiO₂ interfacial layer and a high- κ gate TiLaO dielectric, the TaN/TiLaO/SiO₂ on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm²(V.s)at 0.5 MV/cm, and a very low off-state leakage current of 3.5×10^-10 A/μ. The self-aligned and gate-first metal-gate/high- κ and Ge nMOSFETs were processed using standard ion implantation and 550 °C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.

Original language	English
Article number	5345768
Pages (from-to)	80-82
Number of pages	3
Journal	Ieee Electron Device Letters
Volume	31
Issue number	1
DOIs	https://doi.org/10.1109/LED.2009.2035719
State	Published - Jan 2010

Keywords

Ge
NMOSFETs
TaN
TiLaO

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10.1109/LED.2009.2035719

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abstract = "Using a SiO2 interfacial layer and a high- κ gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm2(V.s)at 0.5 MV/cm, and a very low off-state leakage current of 3.5×10-10 A/μ. The self-aligned and gate-first metal-gate/high- κ and Ge nMOSFETs were processed using standard ion implantation and 550 °C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.",

keywords = "Ge, NMOSFETs, TaN, TiLaO",

author = "Chen, {W. B.} and Albert Chin",

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AU - Chin, Albert

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AB - Using a SiO2 interfacial layer and a high- κ gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm2(V.s)at 0.5 MV/cm, and a very low off-state leakage current of 3.5×10-10 A/μ. The self-aligned and gate-first metal-gate/high- κ and Ge nMOSFETs were processed using standard ion implantation and 550 °C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.

KW - Ge

KW - NMOSFETs

KW - TaN

KW - TiLaO

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JO - Ieee Electron Device Letters

JF - Ieee Electron Device Letters

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M1 - 5345768

ER -

High performance of Ge nMOSFETs Using SiO₂ interfacial layer and TiLaO gate dielectric

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