High-performance NAND flash controller exploiting parallel out-of-order command execution

Yu Hsiang Kao; Juinn-Dar Huang

doi:10.1109/VDAT.2010.5496715

High-performance NAND flash controller exploiting parallel out-of-order command execution

Yu Hsiang Kao^*, Juinn-Dar Huang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

NAND flash memory is one of the most important components in modern non-volatile storage media. However, long command setup time and slow I/O interface frequency of current NAND flash device has been limiting the bandwidth of data transfer. In this paper, we propose a high-performance NAND flash controller architecture by exploiting two techniques - parallel out-of-order execution of multi-die commands and two-plane address translation. By these two techniques, the number of commands being executed in parallel can be maximized and the average execution time per command can thus be greatly reduced to achieve higher performance. The experimental results show that the proposed NAND flash controller can improve the data access performance in both read and program for at least 18% as compared to a baseline NAND flash controller.

Original language	English
Title of host publication	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages	160-163
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2010.5496715
State	Published - 2010
Event	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan Duration: 26 Apr 2010 → 29 Apr 2010

Publication series

Name	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Conference

Conference	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Country/Territory	Taiwan
City	Hsin Chu
Period	26/04/10 → 29/04/10

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10.1109/VDAT.2010.5496715

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Kao, Y. H., & Huang, J.-D. (2010). High-performance NAND flash controller exploiting parallel out-of-order command execution. In Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 (pp. 160-163). Article 5496715 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010). https://doi.org/10.1109/VDAT.2010.5496715

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title = "High-performance NAND flash controller exploiting parallel out-of-order command execution",

abstract = "NAND flash memory is one of the most important components in modern non-volatile storage media. However, long command setup time and slow I/O interface frequency of current NAND flash device has been limiting the bandwidth of data transfer. In this paper, we propose a high-performance NAND flash controller architecture by exploiting two techniques - parallel out-of-order execution of multi-die commands and two-plane address translation. By these two techniques, the number of commands being executed in parallel can be maximized and the average execution time per command can thus be greatly reduced to achieve higher performance. The experimental results show that the proposed NAND flash controller can improve the data access performance in both read and program for at least 18% as compared to a baseline NAND flash controller.",

author = "Kao, {Yu Hsiang} and Juinn-Dar Huang",

year = "2010",

doi = "10.1109/VDAT.2010.5496715",

language = "English",

isbn = "9781424452712",

series = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

pages = "160--163",

booktitle = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

note = "2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 ; Conference date: 26-04-2010 Through 29-04-2010",

}

Kao, YH & Huang, J-D 2010, High-performance NAND flash controller exploiting parallel out-of-order command execution. in Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010., 5496715, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, pp. 160-163, 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, Hsin Chu, Taiwan, 26/04/10. https://doi.org/10.1109/VDAT.2010.5496715

High-performance NAND flash controller exploiting parallel out-of-order command execution. / Kao, Yu Hsiang; Huang, Juinn-Dar.
Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. 2010. p. 160-163 5496715 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - NAND flash memory is one of the most important components in modern non-volatile storage media. However, long command setup time and slow I/O interface frequency of current NAND flash device has been limiting the bandwidth of data transfer. In this paper, we propose a high-performance NAND flash controller architecture by exploiting two techniques - parallel out-of-order execution of multi-die commands and two-plane address translation. By these two techniques, the number of commands being executed in parallel can be maximized and the average execution time per command can thus be greatly reduced to achieve higher performance. The experimental results show that the proposed NAND flash controller can improve the data access performance in both read and program for at least 18% as compared to a baseline NAND flash controller.

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High-performance NAND flash controller exploiting parallel out-of-order command execution

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