High-Performance Junctionless Ferroelectric Thin-Film Transistor for Low-Voltage and High-Speed Nonvolatile Memory Applications

A junctionless ferroelectric thin-film transistor (JL-FeTFT) that combines a highly doped polycrystalline-silicon (poly-Si) channel with a ferroelectric gate insulator is proposed and investigates its nonvolatile memory (NVM) characteristics for application in high-density vertically stacked memory structures in neuromorphic computing. Compared to the conventional inversion mode FeTFT (IM-FeTFT) with undoped poly-Si channel, the JL-FeTFT demonstrates significant advantages. First, the JL-FeTFT operates at a lower voltage due to the higher electron concentration in the channel, resulting in a reduction of the threshold voltage (V_TH) by 0.522 V. Second, the transconductance of JL-FeTFT is 6.28 times higher than that of IM-FeTFT. Additionally, the V_TH modulation in JL-FeTFT is significantly higher than in IM-FeTFT across various pulse widths, particularly excelling under short pulse widths and low operating voltages. Furthermore, the JL-FeTFT exhibits endurance of 2 × 10⁵ cycles at a 300 ns pulsewidth, substantially surpassing the 5 × 10⁴ cycles of the IM-FeTFT. The JL-FeTFT also shows better stability and reliability, with a smaller reduction in the memory window (MW) after up to 106 program/erase (PRG/ERS) cycles. Moreover, after 106 PRG/ERS cycles, the JL-FeTFT maintains lower degradation in ON-current, subthreshold swing (SS), and transconductance compared to the IM-FeTFT. Additionally, the JL-FeTFT operates at lower voltages and achieves endurance of 105 cycles at a 100 ns pulsewidth, making it suitable for high-speed and low-voltage NVM applications. Consequently, the JL-FeTFT demonstrates advantages in terms of low operating voltage, high ON-current, excellent endurance, and reliability, positioning it as a promising candidate for future high-density and high-performance memory.