High-performance 0.6V V MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

Hao I. Yang; Yi Wei Lin; Mao Chih Hsia; Geng Cing Lin; Chi Shin Chang; Yin Nien Chen; Ching Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan Chun Lien; Hung Yu Li; Kuen Di Lee; Wei Chiang Shih; Ya Ping Wu; Wen Ta Lee; Chih Chiang Hsu

doi:10.1109/ISCAS.2012.6271624

High-performance 0.6V V _MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

Hao I. Yang^*, Yi Wei Lin, Mao Chih Hsia, Geng Cing Lin, Chi Shin Chang, Yin Nien Chen, Ching Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan Chun Lien, Hung Yu Li, Kuen Di Lee, Wei Chiang Shih, Ya Ping Wu, Wen Ta Lee, Chih Chiang Hsu

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

This paper presents a 1.0Mb high-performance 0.6V V _MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is [email protected] and [email protected].

Original language	English
Pages	1831-1834
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271624
State	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6271624

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Yang, H. I., Lin, Y. W., Hsia, M. C., Lin, G. C., Chang, C. S., Chen, Y. N., Chuang, C. T., Hwang, W., Jou, S.-J., Lien, N. C., Li, H. Y., Lee, K. D., Shih, W. C., Wu, Y. P., Lee, W. T., & Hsu, C. C. (2012). High-performance 0.6V V _MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. 1831-1834. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271624

@conference{1162bcc1fb1d4cf79ddfd8730ce92a3c,

title = "High-performance 0.6V V MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder",

abstract = "This paper presents a 1.0Mb high-performance 0.6V V MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is [email protected] and [email protected].",

author = "Yang, {Hao I.} and Lin, {Yi Wei} and Hsia, {Mao Chih} and Lin, {Geng Cing} and Chang, {Chi Shin} and Chen, {Yin Nien} and Chuang, {Ching Te} and Wei Hwang and Shyh-Jye Jou and Lien, {Nan Chun} and Li, {Hung Yu} and Lee, {Kuen Di} and Shih, {Wei Chiang} and Wu, {Ya Ping} and Lee, {Wen Ta} and Hsu, {Chih Chiang}",

year = "2012",

doi = "10.1109/ISCAS.2012.6271624",

language = "English",

pages = "1831--1834",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

Yang, HI, Lin, YW, Hsia, MC, Lin, GC, Chang, CS, Chen, YN, Chuang, CT, Hwang, W, Jou, S-J, Lien, NC, Li, HY, Lee, KD, Shih, WC, Wu, YP, Lee, WT & Hsu, CC 2012, 'High-performance 0.6V V _MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder', Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 20/05/12 - 23/05/12 pp. 1831-1834. https://doi.org/10.1109/ISCAS.2012.6271624

TY - CONF

T1 - High-performance 0.6V V MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

AU - Yang, Hao I.

AU - Lin, Yi Wei

AU - Hsia, Mao Chih

AU - Lin, Geng Cing

AU - Chang, Chi Shin

AU - Chen, Yin Nien

AU - Chuang, Ching Te

AU - Hwang, Wei

AU - Jou, Shyh-Jye

AU - Lien, Nan Chun

AU - Li, Hung Yu

AU - Lee, Kuen Di

AU - Shih, Wei Chiang

AU - Wu, Ya Ping

AU - Lee, Wen Ta

AU - Hsu, Chih Chiang

PY - 2012

Y1 - 2012

N2 - This paper presents a 1.0Mb high-performance 0.6V V MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is [email protected] and [email protected].

AB - This paper presents a 1.0Mb high-performance 0.6V V MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is [email protected] and [email protected].

UR - http://www.scopus.com/inward/record.url?scp=84866624700&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271624

DO - 10.1109/ISCAS.2012.6271624

M3 - Paper

AN - SCOPUS:84866624700

SP - 1831

EP - 1834

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

High-performance 0.6V V _MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

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