High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

Wen Quan He, Yuan Ho Chen, Shyh-Jye Jou

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    13 Scopus citations

    Abstract

    This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-μm CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

    Original languageEnglish
    Article number7166389
    Pages (from-to)2052-2061
    Number of pages10
    JournalIEEE Transactions on Circuits and Systems I: Regular Papers
    Volume62
    Issue number8
    DOIs
    StatePublished - 1 Aug 2015

    Keywords

    • Booth encoder
    • dynamic error-compensation
    • fixed-width multiplier
    • mathematical probable model

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