Abstract
The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( text{R}{text {ON}} ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max-min ratio ( {G}{text {MAX}}/ ∼{G}{text {MIN}} ; 50), low nonlinearity of alpha{text {p}} = -0.81 and alpha{text {d}} = -0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.
Original language | English |
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Article number | 9206053 |
Pages (from-to) | 1649-1652 |
Number of pages | 4 |
Journal | Ieee Electron Device Letters |
Volume | 41 |
Issue number | 11 |
DOIs | |
State | Published - Nov 2020 |
Keywords
- Charge-trap memory
- contralateral-gated
- MoS2
- neural networks
- nonvolatile
- transition metal dichalcogenide (TMD)