Hierarchical techniques for symbolic analysis of large electronic circuits

Shyh-Jye Jou; Mei Fang Perng; Chau-Chin Su; C. K. Wang

doi:10.1109/ISCAS.1994.408745

Hierarchical techniques for symbolic analysis of large electronic circuits

Shyh-Jye Jou^*, Mei Fang Perng, Chau-Chin Su, C. K. Wang

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

A hierarchical symbolic analyzer(SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.

Original language	English
Pages (from-to)	21-24
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/ISCAS.1994.408745
State	Published - 1 Dec 1994
Event	Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: 30 May 1994 → 2 Jun 1994

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10.1109/ISCAS.1994.408745

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title = "Hierarchical techniques for symbolic analysis of large electronic circuits",

abstract = "A hierarchical symbolic analyzer(SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.",

author = "Shyh-Jye Jou and Perng, {Mei Fang} and Chau-Chin Su and Wang, {C. K.}",

year = "1994",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "null ; Conference date: 30-05-1994 Through 02-06-1994",

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AU - Jou, Shyh-Jye

AU - Perng, Mei Fang

AU - Su, Chau-Chin

AU - Wang, C. K.

PY - 1994/12/1

Y1 - 1994/12/1

N2 - A hierarchical symbolic analyzer(SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.

AB - A hierarchical symbolic analyzer(SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.

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U2 - 10.1109/ISCAS.1994.408745

DO - 10.1109/ISCAS.1994.408745

M3 - Conference article

AN - SCOPUS:0028554088

VL - 1

SP - 21

EP - 24

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

Y2 - 30 May 1994 through 2 June 1994

ER -

Hierarchical techniques for symbolic analysis of large electronic circuits

Abstract

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