Hierarchical instruction encoding for VLIW digital signal processors

Chia Hsien Liu; Tay Jyi Lin; Chie Min Chao; Pi Chen Hsiao; Li Chun Lin; Shin Kai Chen; Chao Wei Huang; Chih-Wei Liu; Chein Wei Jen

doi:10.1109/ISCAS.2005.1465384

Hierarchical instruction encoding for VLIW digital signal processors

Chia Hsien Liu, Tay Jyi Lin, Chie Min Chao, Pi Chen Hsiao, Li Chun Lin, Shin Kai Chen, Chao Wei Huang, Chih-Wei Liu, Chein Wei Jen

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

VLIW-based architectures are very popular in highperformance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixedlength instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%̃66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.

Original language	English
Article number	1465384
Pages (from-to)	3503-3506
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465384
State	Published - 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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title = "Hierarchical instruction encoding for VLIW digital signal processors",

abstract = "VLIW-based architectures are very popular in highperformance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixedlength instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4{\~%}66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.",

author = "Liu, {Chia Hsien} and Lin, {Tay Jyi} and Chao, {Chie Min} and Hsiao, {Pi Chen} and Lin, {Li Chun} and Chen, {Shin Kai} and Huang, {Chao Wei} and Chih-Wei Liu and Jen, {Chein Wei}",

year = "2005",

doi = "10.1109/ISCAS.2005.1465384",

language = "English",

pages = "3503--3506",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

}

TY - JOUR

T1 - Hierarchical instruction encoding for VLIW digital signal processors

AU - Liu, Chia Hsien

AU - Lin, Tay Jyi

AU - Chao, Chie Min

AU - Hsiao, Pi Chen

AU - Lin, Li Chun

AU - Chen, Shin Kai

AU - Huang, Chao Wei

AU - Liu, Chih-Wei

AU - Jen, Chein Wei

PY - 2005

Y1 - 2005

N2 - VLIW-based architectures are very popular in highperformance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixedlength instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%̃66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.

AB - VLIW-based architectures are very popular in highperformance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixedlength instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%̃66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.

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U2 - 10.1109/ISCAS.2005.1465384

DO - 10.1109/ISCAS.2005.1465384

M3 - Conference article

AN - SCOPUS:34547155045

SN - 0271-4310

SP - 3503

EP - 3506

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1465384

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

Hierarchical instruction encoding for VLIW digital signal processors

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