@inproceedings{b362798fb2dd43c88dc4d035065ee73b,
title = "Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation",
abstract = "This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm2 in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.",
keywords = "and hardware implementation, Blind signal separation, component/channel switch, EEG, fast independent component analysis (FastICA)",
author = "Lan-Da Van and Lu, {Tsung Che} and Jung, {Tzyy Ping} and Wang, {Jo Fu}",
year = "2019",
month = may,
day = "1",
doi = "10.1109/ICASSP.2019.8682997",
language = "English",
series = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1438--1442",
booktitle = "2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings",
address = "United States",
note = "44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 ; Conference date: 12-05-2019 Through 17-05-2019",
}