Hardware nested looping of parameterized and embedded DSP core

Ya Lan Tsao, Wei Hao Chen, Wen Sheng Cheng, Maw Ching Lin, Shyh-Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations


In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2003
EditorsDong S. Ha, Richard Auletta, John Chickanosky
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780381823, 9780780381827
StatePublished - 1 Jan 2003
EventIEEE International SOC Conference, SOCC 2003 - Portland, United States
Duration: 17 Sep 200320 Sep 2003

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2003


ConferenceIEEE International SOC Conference, SOCC 2003
Country/TerritoryUnited States


  • Application specific integrated circuits
  • Cities and towns
  • Communication system control
  • Digital signal processing
  • Digital signal processing chips
  • Energy consumption
  • Hardware
  • Hazards
  • Pipelines
  • Signal processing algorithms


Dive into the research topics of 'Hardware nested looping of parameterized and embedded DSP core'. Together they form a unique fingerprint.

Cite this