Hardware nested looping of parameterized and embedded DSP core

Ya Lan Tsao; Wei Hao Chen; Wen Sheng Cheng; Maw Ching Lin; Shyh-Jye Jou

doi:10.1109/SOC.2003.1241460

Hardware nested looping of parameterized and embedded DSP core

Ya Lan Tsao, Wei Hao Chen, Wen Sheng Cheng, Maw Ching Lin, Shyh-Jye Jou

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2003
Editors	Dong S. Ha, Richard Auletta, John Chickanosky
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	49-52
Number of pages	4
ISBN (Electronic)	0780381823, 9780780381827
DOIs	https://doi.org/10.1109/SOC.2003.1241460
State	Published - 1 Jan 2003
Event	IEEE International SOC Conference, SOCC 2003 - Portland, United States Duration: 17 Sep 2003 → 20 Sep 2003

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2003

Conference

Conference	IEEE International SOC Conference, SOCC 2003
Country/Territory	United States
City	Portland
Period	17/09/03 → 20/09/03

Keywords

Application specific integrated circuits
Cities and towns
Communication system control
Digital signal processing
Digital signal processing chips
Energy consumption
Hardware
Hazards
Pipelines
Signal processing algorithms

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/SOC.2003.1241460

Cite this

Tsao, Y. L., Chen, W. H., Cheng, W. S., Lin, M. C., & Jou, S.-J. (2003). Hardware nested looping of parameterized and embedded DSP core. In D. S. Ha, R. Auletta, & J. Chickanosky (Eds.), Proceedings - IEEE International SOC Conference, SOCC 2003 (pp. 49-52). Article 1241460 (Proceedings - IEEE International SOC Conference, SOCC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOC.2003.1241460

Tsao, Ya Lan ; Chen, Wei Hao ; Cheng, Wen Sheng et al. / Hardware nested looping of parameterized and embedded DSP core. Proceedings - IEEE International SOC Conference, SOCC 2003. editor / Dong S. Ha ; Richard Auletta ; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 49-52 (Proceedings - IEEE International SOC Conference, SOCC 2003).

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title = "Hardware nested looping of parameterized and embedded DSP core",

abstract = "In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.",

keywords = "Application specific integrated circuits, Cities and towns, Communication system control, Digital signal processing, Digital signal processing chips, Energy consumption, Hardware, Hazards, Pipelines, Signal processing algorithms",

author = "Tsao, {Ya Lan} and Chen, {Wei Hao} and Cheng, {Wen Sheng} and Lin, {Maw Ching} and Shyh-Jye Jou",

year = "2003",

month = jan,

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doi = "10.1109/SOC.2003.1241460",

language = "English",

series = "Proceedings - IEEE International SOC Conference, SOCC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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editor = "Ha, {Dong S.} and Richard Auletta and John Chickanosky",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2003",

address = "美國",

note = "IEEE International SOC Conference, SOCC 2003 ; Conference date: 17-09-2003 Through 20-09-2003",

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Tsao, YL, Chen, WH, Cheng, WS, Lin, MC & Jou, S-J 2003, Hardware nested looping of parameterized and embedded DSP core. in DS Ha, R Auletta & J Chickanosky (eds), Proceedings - IEEE International SOC Conference, SOCC 2003., 1241460, Proceedings - IEEE International SOC Conference, SOCC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 49-52, IEEE International SOC Conference, SOCC 2003, Portland, United States, 17/09/03. https://doi.org/10.1109/SOC.2003.1241460

Hardware nested looping of parameterized and embedded DSP core. / Tsao, Ya Lan; Chen, Wei Hao; Cheng, Wen Sheng et al.
Proceedings - IEEE International SOC Conference, SOCC 2003. ed. / Dong S. Ha; Richard Auletta; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. p. 49-52 1241460 (Proceedings - IEEE International SOC Conference, SOCC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.

KW - Application specific integrated circuits

KW - Cities and towns

KW - Communication system control

KW - Digital signal processing

KW - Digital signal processing chips

KW - Energy consumption

KW - Hardware

KW - Hazards

KW - Pipelines

KW - Signal processing algorithms

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BT - Proceedings - IEEE International SOC Conference, SOCC 2003

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Tsao YL, Chen WH, Cheng WS, Lin MC, Jou SJ. Hardware nested looping of parameterized and embedded DSP core. In Ha DS, Auletta R, Chickanosky J, editors, Proceedings - IEEE International SOC Conference, SOCC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 49-52. 1241460. (Proceedings - IEEE International SOC Conference, SOCC 2003). doi: 10.1109/SOC.2003.1241460

Hardware nested looping of parameterized and embedded DSP core

Abstract

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Conference

Keywords

UN SDGs

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