Hardware-efficient pipelined programmable FIR filter design

Tian-Sheuan Chang*, C. W. Jen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


With the increasing demand for video-signal processing and transmission, high-speed programmable FIR filters are required for real-time processing. This paper presents a hardware-efficient pipelined FIR architecture with programmable coefficients. FIR operations are first reformulated into multi-bit DA form at an algorithm level. Then, at the architecture level, the (p, q) compressor, instead of Booth encoding or RAM implementation, is used for high-speed operation. Due to the simple architecture, we can easily pipeline the proposed FIR filter to the adder level and save up to half of the cost of previous designs without sacrificing performance. The presented design is useful for bit-parallel input design, which can save 36.7% of the area cost compared with previous approaches.

Original languageEnglish
Pages (from-to)227-232
Number of pages6
JournalIEE Proceedings: Computers and Digital Techniques
Issue number6
StatePublished - Nov 2001


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