Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs

Keyphrases

• Hardware Efficiency 100%
• Efficient Implementation 100%
• Distributed Arithmetic 100%
• Discrete Function 100%
• Hardware Cost 66%
• Bit Level 66%
• FPGA Device 66%
• Proposed Design 33%
• Multiplierless 33%
• Grain Size 33%
• Device Characteristics 33%
• Algorithmic Level 33%
• Input Buffer 33%
• Buffer Design 33%

Engineering

• Field Programmable Gate Arrays 100%
• Efficient Implementation 100%
• Hardware Cost 50%
• Adders 25%
• Algorithm Level 25%
• Input Buffer 25%
• Free Design 25%
• Grain Level 25%