TY - GEN
T1 - Hardware accelerated inverse kinematics for low power surgical manipulators
AU - Tkachenko, Oleksii
AU - Song, Kai Tai
N1 - Publisher Copyright:
© 2020 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/8
Y1 - 2020/8
N2 - Robotic minimally invasive surgery (MIS) is performed via small incisions and so lessens wound healing time, associated pain and risk of infection. We refactor the control pipeline and accelerate the most time-consuming stage- inverse kinematics (IK) calculation for robot assisted MIS. Field programmable gate array (FPGA) technology is used to develop a low power hardware IK accelerator. The set of optimization techniques reduces the design's size so it can fit onto the real hardware. Accelerator executes IK in approximately 30 microseconds. System architecture runs on a heterogeneous CPUFPGA platform. Single and multi-point architectures are developed, where multi-point architecture overcomes communication overhead between platforms and allows achieving a higher output rate. Implementation is tested for 16, 24 and 32-bit fixed-point numbers, with an average computation error of 0.07 millimeters for 32-bit architecture. Experimental results validate and verify the proposed solution.
AB - Robotic minimally invasive surgery (MIS) is performed via small incisions and so lessens wound healing time, associated pain and risk of infection. We refactor the control pipeline and accelerate the most time-consuming stage- inverse kinematics (IK) calculation for robot assisted MIS. Field programmable gate array (FPGA) technology is used to develop a low power hardware IK accelerator. The set of optimization techniques reduces the design's size so it can fit onto the real hardware. Accelerator executes IK in approximately 30 microseconds. System architecture runs on a heterogeneous CPUFPGA platform. Single and multi-point architectures are developed, where multi-point architecture overcomes communication overhead between platforms and allows achieving a higher output rate. Implementation is tested for 16, 24 and 32-bit fixed-point numbers, with an average computation error of 0.07 millimeters for 32-bit architecture. Experimental results validate and verify the proposed solution.
UR - http://www.scopus.com/inward/record.url?scp=85092592830&partnerID=8YFLogxK
U2 - 10.1109/ARIS50834.2020.9205769
DO - 10.1109/ARIS50834.2020.9205769
M3 - Conference contribution
AN - SCOPUS:85092592830
T3 - International Conference on Advanced Robotics and Intelligent Systems, ARIS
BT - 2020 International Conference on Advanced Robotics and Intelligent Systems, ARIS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 International Conference on Advanced Robotics and Intelligent Systems, ARIS 2020
Y2 - 19 August 2020 through 21 August 2020
ER -