Halo and LDD engineering for multiple vTH high performance analog CMOS devices

Jyh-Chyurn Guo*

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    4 Scopus citations

    Abstract

    High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-μm logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.

    Original languageEnglish
    Pages (from-to)313-321
    Number of pages9
    JournalIEEE Transactions on Semiconductor Manufacturing
    Volume20
    Issue number3
    DOIs
    StatePublished - 1 Aug 2007

    Keywords

    • Dual gate oxide
    • Halo
    • High performance analog (HPA)
    • LDD engineering
    • Multiple threshold voltages

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