Grain boundary trap-induced current transient in a 3-D NAND flash cell string

Wei Liang Lin; Wen Jer Tsai; C. C. Cheng; S. H. Ku; Lenvis Liu; S. W. Hwang; Tao Cheng Lu; Kuang Chao Chen; Tseung-Yuen Tseng; Chih Yuan Lu

doi:10.1109/TED.2019.2900736

Grain boundary trap-induced current transient in a 3-D NAND flash cell string

Wei Liang Lin^*, Wen Jer Tsai, C. C. Cheng, S. H. Ku, Lenvis Liu, S. W. Hwang, Tao Cheng Lu, Kuang Chao Chen, Tseung-Yuen Tseng, Chih Yuan Lu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 μs or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in 'pseudo' charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.

Original language	English
Article number	8666060
Pages (from-to)	1734-1740
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	4
DOIs	https://doi.org/10.1109/TED.2019.2900736
State	Published - 1 Apr 2019

Keywords

3-D NAND flash
cell current/threshold voltage instability
gate-all-around (GAA)
grain boundary trap (GBT)
nonvolatile memory
polycrystalline silicon channel
program verify (PV)
transient
trapping/detrapping

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10.1109/TED.2019.2900736

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title = "Grain boundary trap-induced current transient in a 3-D NAND flash cell string",

abstract = "Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 μs or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in 'pseudo' charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.",

keywords = "3-D NAND flash, cell current/threshold voltage instability, gate-all-around (GAA), grain boundary trap (GBT), nonvolatile memory, polycrystalline silicon channel, program verify (PV), transient, trapping/detrapping",

author = "Lin, {Wei Liang} and Tsai, {Wen Jer} and Cheng, {C. C.} and Ku, {S. H.} and Lenvis Liu and Hwang, {S. W.} and Lu, {Tao Cheng} and Chen, {Kuang Chao} and Tseung-Yuen Tseng and Lu, {Chih Yuan}",

year = "2019",

month = apr,

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doi = "10.1109/TED.2019.2900736",

language = "English",

volume = "66",

pages = "1734--1740",

journal = "Ieee Transactions On Electron Devices",

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T1 - Grain boundary trap-induced current transient in a 3-D NAND flash cell string

AU - Lin, Wei Liang

AU - Tsai, Wen Jer

AU - Cheng, C. C.

AU - Ku, S. H.

AU - Liu, Lenvis

AU - Hwang, S. W.

AU - Lu, Tao Cheng

AU - Chen, Kuang Chao

AU - Tseng, Tseung-Yuen

AU - Lu, Chih Yuan

PY - 2019/4/1

Y1 - 2019/4/1

N2 - Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 μs or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in 'pseudo' charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.

AB - Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 μs or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in 'pseudo' charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.

KW - 3-D NAND flash

KW - cell current/threshold voltage instability

KW - gate-all-around (GAA)

KW - grain boundary trap (GBT)

KW - nonvolatile memory

KW - polycrystalline silicon channel

KW - program verify (PV)

KW - transient

KW - trapping/detrapping

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U2 - 10.1109/TED.2019.2900736

DO - 10.1109/TED.2019.2900736

M3 - Article

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SN - 0018-9383

VL - 66

SP - 1734

EP - 1740

JO - Ieee Transactions On Electron Devices

JF - Ieee Transactions On Electron Devices

IS - 4

M1 - 8666060

ER -

Grain boundary trap-induced current transient in a 3-D NAND flash cell string

Abstract

Keywords

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