Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Chun-Jung Su; T. C. Hong; Y. C. Tsou; F. J. Hou; P. J. Sung; M. S. Yeh; C. C. Wan; K. H. Kao; Y. T. Tang; C. H. Chiu; C. J. Wang; S. T. Chung; T. Y. You; Y. C. Huang; C. T. Wu; K. L. Lin; G. L. Luo; K. P. Huang; Y. J. Lee; Tien-Sheng Chao; W. F. Wu; G. W. Huang; J. M. Shieh; W. K. Yeh; Y. H. Wang

doi:10.1109/IEDM.2017.8268396

Ge nanowire FETs with HfZrO_x ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Chun-Jung Su, T. C. Hong, Y. C. Tsou, F. J. Hou, P. J. Sung, M. S. Yeh, C. C. Wan, K. H. Kao, Y. T. Tang, C. H. Chiu, C. J. Wang, S. T. Chung, T. Y. You, Y. C. Huang, C. T. Wu, K. L. Lin, G. L. Luo, K. P. Huang, Y. J. Lee, Tien-Sheng ChaoW. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Y. H. Wang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 10⁷ and 10⁶ for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.

Original language	English
Title of host publication	2017 IEEE International Electron Devices Meeting, IEDM 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	15.4.1-15.4.4
Number of pages	4
ISBN (Electronic)	9781538635599
DOIs	https://doi.org/10.1109/IEDM.2017.8268396
State	Published - 2 Dec 2017
Event	63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States Duration: 2 Dec 2017 → 6 Dec 2017

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	63rd IEEE International Electron Devices Meeting, IEDM 2017
Country/Territory	United States
City	San Francisco
Period	2/12/17 → 6/12/17

Access to Document

10.1109/IEDM.2017.8268396

Cite this

Su, C.-J., Hong, T. C., Tsou, Y. C., Hou, F. J., Sung, P. J., Yeh, M. S., Wan, C. C., Kao, K. H., Tang, Y. T., Chiu, C. H., Wang, C. J., Chung, S. T., You, T. Y., Huang, Y. C., Wu, C. T., Lin, K. L., Luo, G. L., Huang, K. P., Lee, Y. J., ... Wang, Y. H. (2017). Ge nanowire FETs with HfZrO_x ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability. In 2017 IEEE International Electron Devices Meeting, IEDM 2017 (pp. 15.4.1-15.4.4). Article 8268396 (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2017.8268396

Su, Chun-Jung ; Hong, T. C. ; Tsou, Y. C. et al. / Ge nanowire FETs with HfZrO_x ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability. 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 15.4.1-15.4.4 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{6ee573e297ab434d877b7fdfcb27f5a2,

title = "Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability",

abstract = "Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 107 and 106 for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.",

author = "Chun-Jung Su and Hong, {T. C.} and Tsou, {Y. C.} and Hou, {F. J.} and Sung, {P. J.} and Yeh, {M. S.} and Wan, {C. C.} and Kao, {K. H.} and Tang, {Y. T.} and Chiu, {C. H.} and Wang, {C. J.} and Chung, {S. T.} and You, {T. Y.} and Huang, {Y. C.} and Wu, {C. T.} and Lin, {K. L.} and Luo, {G. L.} and Huang, {K. P.} and Lee, {Y. J.} and Tien-Sheng Chao and Wu, {W. F.} and Huang, {G. W.} and Shieh, {J. M.} and Yeh, {W. K.} and Wang, {Y. H.}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 63rd IEEE International Electron Devices Meeting, IEDM 2017 ; Conference date: 02-12-2017 Through 06-12-2017",

year = "2017",

month = dec,

day = "2",

doi = "10.1109/IEDM.2017.8268396",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "15.4.1--15.4.4",

booktitle = "2017 IEEE International Electron Devices Meeting, IEDM 2017",

address = "美國",

}

Su, C-J, Hong, TC, Tsou, YC, Hou, FJ, Sung, PJ, Yeh, MS, Wan, CC, Kao, KH, Tang, YT, Chiu, CH, Wang, CJ, Chung, ST, You, TY, Huang, YC, Wu, CT, Lin, KL, Luo, GL, Huang, KP, Lee, YJ, Chao, T-S, Wu, WF, Huang, GW, Shieh, JM, Yeh, WK & Wang, YH 2017, Ge nanowire FETs with HfZrO_x ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability. in 2017 IEEE International Electron Devices Meeting, IEDM 2017., 8268396, Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., pp. 15.4.1-15.4.4, 63rd IEEE International Electron Devices Meeting, IEDM 2017, San Francisco, United States, 2/12/17. https://doi.org/10.1109/IEDM.2017.8268396

Ge nanowire FETs with HfZrO_x ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability. / Su, Chun-Jung; Hong, T. C.; Tsou, Y. C. et al.
2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 15.4.1-15.4.4 8268396 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

AU - Su, Chun-Jung

AU - Hong, T. C.

AU - Tsou, Y. C.

AU - Hou, F. J.

AU - Sung, P. J.

AU - Yeh, M. S.

AU - Wan, C. C.

AU - Kao, K. H.

AU - Tang, Y. T.

AU - Chiu, C. H.

AU - Wang, C. J.

AU - Chung, S. T.

AU - You, T. Y.

AU - Huang, Y. C.

AU - Wu, C. T.

AU - Lin, K. L.

AU - Luo, G. L.

AU - Huang, K. P.

AU - Lee, Y. J.

AU - Chao, Tien-Sheng

AU - Wu, W. F.

AU - Huang, G. W.

AU - Shieh, J. M.

AU - Yeh, W. K.

AU - Wang, Y. H.

PY - 2017/12/2

Y1 - 2017/12/2

N2 - Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 107 and 106 for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.

AB - Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 107 and 106 for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.

UR - http://www.scopus.com/inward/record.url?scp=85045207012&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2017.8268396

DO - 10.1109/IEDM.2017.8268396

M3 - Conference contribution

AN - SCOPUS:85045207012

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 15.4.1-15.4.4

BT - 2017 IEEE International Electron Devices Meeting, IEDM 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 63rd IEEE International Electron Devices Meeting, IEDM 2017

Y2 - 2 December 2017 through 6 December 2017

ER -

Su CJ, Hong TC, Tsou YC, Hou FJ, Sung PJ, Yeh MS et al. Ge nanowire FETs with HfZrO_x ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability. In 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 15.4.1-15.4.4. 8268396. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2017.8268396