Gate Voltages Impacting on Latch-up Measurements

Shao Chang Huang, Jian Hsing Lee, Chun Chih Chen, Ching Ho Li, Chih Cherng Liao, Kai Chieh Hsu, Gong Kai Lin, Li Fan Chen, Chien Wei Wang, Chih Hsuan Lin, Yeh Ning Jou, Ke Horng Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Integrated Circuits (ICs) are often turned off under latch-up measurements. One power IC is often applied with a large size for driving capabilities. The large size device is often difficult to be turned off under latch-up stresses. In this paper, device behaviors of different gate biased voltages applied on large size devices under latch-up measurements are discussed. From the silicon data analyses, latch-up current paths changed from MOSFET to the parasitic diodes are observed well so the false latch-up test is verified. Finally, over voltage test is proposed for turned-on large size devices' latch-up measurements.

Original languageEnglish
Title of host publicationProceedings - 2022 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages75-76
Number of pages2
ISBN (Electronic)9781665470506
DOIs
StatePublished - 2022
Event2022 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2022 - Taipei, Taiwan
Duration: 6 Jul 20228 Jul 2022

Publication series

NameProceedings - 2022 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2022

Conference

Conference2022 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2022
Country/TerritoryTaiwan
CityTaipei
Period6/07/228/07/22

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