Gate-stack engineering for self-organized Ge-dot/SiO ₂ /SiGe-shell MOS capacitors

We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO ₂ /SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si ₃ N ₄ buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5–90 nm), the SiO ₂ thickness (3–4 nm), and the SiGe-shell thickness (2–15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO ₂ /Ge-dot and SiO ₂ /SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO ₂ /SiGe and Al/SiO ₂ /Ge-dot/SiO ₂ /SiGe MOS capacitors exhibit low interface trap densities of as low as 3–5 × 10 ¹¹ cm ⁻² eV ⁻¹ and fixed charge densities of 1–5 × 10 ¹¹ cm ⁻² , suggesting good-quality SiO ₂ /SiGe-shell and SiO ₂ /Ge-dot interfaces. In addition, the advantage of having single-crystalline Si _{1− x} Ge _x shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.