Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices

Wei Ting Lai, Kuo Ching Yang, Po Hsiang Liao, Thomas George, Pei-Wen Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGe-channel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO2 and SiO2/SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO2/Ge-nanospheres and NiGe/SiO2/SiGe MOS capacitors exhibit quite low interface trap densities of 3-5×1011 cm-2eV1, which is beneficial for advanced Ge MOS applications.

Original languageEnglish
Title of host publication2015 Silicon Nanoelectronics Workshop, SNW 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863485389
StatePublished - 24 Sep 2015
EventSilicon Nanoelectronics Workshop, SNW 2015 - Kyoto, Japan
Duration: 14 Jun 201515 Jun 2015

Publication series

Name2015 Silicon Nanoelectronics Workshop, SNW 2015

Conference

ConferenceSilicon Nanoelectronics Workshop, SNW 2015
Country/TerritoryJapan
CityKyoto
Period14/06/1515/06/15

Keywords

  • Capacitance-voltage characteristics
  • Capacitors
  • Logic gates
  • Oxidation
  • Silicon
  • Silicon germanium
  • Substrates

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