@inproceedings{9b377b8365f14c46b97ceda6149e6f4d,
title = "Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices",
abstract = "We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGe-channel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO2 and SiO2/SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO2/Ge-nanospheres and NiGe/SiO2/SiGe MOS capacitors exhibit quite low interface trap densities of 3-5×1011 cm-2eV1, which is beneficial for advanced Ge MOS applications.",
keywords = "Capacitance-voltage characteristics, Capacitors, Logic gates, Oxidation, Silicon, Silicon germanium, Substrates",
author = "Lai, {Wei Ting} and Yang, {Kuo Ching} and Liao, {Po Hsiang} and Thomas George and Pei-Wen Li",
note = "Publisher Copyright: {\textcopyright} 2015 JSAP.; Silicon Nanoelectronics Workshop, SNW 2015 ; Conference date: 14-06-2015 Through 15-06-2015",
year = "2015",
month = sep,
day = "24",
language = "English",
series = "2015 Silicon Nanoelectronics Workshop, SNW 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 Silicon Nanoelectronics Workshop, SNW 2015",
address = "美國",
}